User manual ABIT AT7 V10

[. . . ] Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. Product names appearing in this manual are for identification purpose only and trademarks and product names or brand names appearing in this document are the property of their respective owners. [. . . ] AGP Master 1 WS Write: Two options are available: Disabled or Enabled. This implements a single delay when writing to the AGP Bus. When you set it to Enabled, two-wait states are used by the system, allowing for greater stability. AGP Master 1 WS Read: Two options are available: Disabled or Enabled. This implements a single delay when reading to the AGP Bus. When you set it to Enabled, two-wait states are used by the system, allowing for greater stability. CPU & PCI Bus Control: This item can let you sets several items concerning the PCI parameters. If you do not understand what each item does, please keep the default settings as well. Wrong settings will cause system unstablity. Figure 3-5D. CPU & PCI Bus Control Screen PCI Master Read Caching: Two options are available: Disabled or Enabled. This item can set PCI bus master read use cache function. PCI Master Bus Time-Out: Eight options are available: Disabled ( 001 ( 010 ( 011 ( 100 ( 101 ( 110 (111. It can set the time-out period, when after the set time-out period, PCI bus master will force into arbitration. User's Manual 3-20 Chapter 3 Master Priority Control: Four options are available: Disabled ( 01 ( 10 ( 11. The full named of thius item is Master Priority Rotation Control. When setting to "01", the CPU will always be granted access after the current bus master completes, no matter how many PCI masters are requesting. With setting to "10", if other PCI masters are requesting during the current PCI master grant, the highest priority master will get the bus after the current master completes. But the CPU will be guaranteed to get the bus after that master completes. With setting to "11", if other PCI masters are requesting, the highest priority will get the bus next, then the next highest priority will get the bus, then the CPU will get the bus. In other words, with the above settings, even if multiple PCI masters are continuously requesting the bus, the CPU is guaranteed to get access after every master grant (01), after every other master grant (10) or after every third master grant (11). PCI1 Master 0 WS Write: Two options are available: Enabled or Disabled. When Enabled, writes to the PCI1 bus are executed with zero wait state (immediately) when PCI1 bus is ready to receive data. If it is set to Disabled, the system will wait one state before data is written to the PCI1 bus. PCI2 Master 0 WS Write: Two options are available: Enabled or Disabled. [. . . ] If you feel that you need to contact ABIT directly you can send email to the ABIT technical support department. First, please contact the support team for the branch office closest to you. They will be more familiar with local conditions and problems and will have better insight as to which resellers offer what products and services. Due to the huge number of emails coming in every day and other reasons, such as the time required for problem reproduction, we will not be able to reply to every email. [. . . ]