User manual ALTIUM FPGA TO PCB

[. . . ] FPGA to PCB Training Module Software, documentation and related materials: Copyright © 2006 Altium Limited. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. [. . . ] As a rule of thumb it is best to select the "Tie to individual ports" for Special Function Pins even if you don't intend to use them in the final design. If you need to use an I/O pin that has a special function net label attached to it, just remove the special function net label and replace it with the net label for the net that you do wish to be connected. Selecting any other option other than the "Tie to individual ports" will cause special function net labels to be ripped up or renamed. Beware! 4. 11 Recreating the autogenerated sheet The Synchronize dialog provides a button to Recreate Autogenerated Sheet. This feature should be used under extreme care. If there are any PCB design changes that are yet to have been propagated back to the FPGA project then they can be destroyed once the autogenerated sheet is recreated. Figure 33. Recreating the autogenerated sheet from the synchronize dialog. Recall our previous warning about the nature of special function pins; selecting any other option other than the Tie to individual ports will cause special function net labels to be ripped up or renamed. Beware! 7 - 24 Altium Designer Training Module FPGA to PCB 5. Maintaining project synchronization Maintaining synchronization between an FPGA project and its parent PCB project is greatly improved through the internal synchronization mechanisms that operate within the DXP platform. It is important, however, that users understand how this synchronization process works so that they don't inadvertently make design changes that will defeat project synchronization. 5. 1 The FPGA workspace map At any given time during the design process, the status of the linking between FPGA and PCB projects can be readily checked by launching the FPGA Workspace Map dialog. Access to this dialog is provided by choosing the command of the same name from the Projects menu, or by pressing the button on the Projects panel. In the example below the FPGA Workspace Map displays the relationships (links) between various elements of FPGA and PCB projects and the status of these links ­ whether the two sides of a link are synchronized and up-to-date or whether some action is required to resynchronize them. Figure 34. The FPGA workspace map dialog. The various elements in the two project types are linked in a logical flow ­ from a soft core microcontroller placed within an FPGA project, to a PCB design document within a linked PCB project. Each of the links are summarized as follows: 5. 1. 1 FPGA project ­ soft processor The Soft Processors region of the dialog is purely added for completeness and offers at-a-glance information on the core microcontroller(s) that are being used in a particular FPGA project. The link, as such, is therefore cosmetic. It will always be displayed as synchronized. 5. 1. 2 Schematic document (PCB project) ­ FPGA project This link reflects the synchronized status between the FPGA component in the PCB project and the appropriate configuration in the FPGA project. When determining the status, the software is looking for any net-related changes. 7 - 25 Altium Designer Training Module FPGA to PCB 5. 1. 3 PCB document ­ schematic document (PCB project) This link reflects the synchronized status between the FPGA Component footprint on the PCB document and the FPGA Component symbol on the schematic sheet, both within the PCB project. 5. 1. 4 Link status A link can appear in one of two colors and hovering over a link will produce a textual description of its status: The green link signifies up to date (i. e. The red link signifies that the two sides of the link are not fully synchronized (i. e. a design change has been made on one side but has yet to be passed to the other). Clicking on a schematic-FPGA project link with this status will open the Synchronize dialog, from where you can browse and match any unmatched ports and pins. Figure 35. Determining the link status When two elements of the map are shown to be un-synchronized (i. e. [. . . ] On power up, the FPGA device observes that it is connected to the configuration device and automatically configures itself from the device. In this final exercise we will program the 7 - 51 Altium Designer Training Module FPGA to PCB configuration device and make the spirit level a truly self-contained embedded system. This exercise flows on from the previous one. Any calibration factors incorporated into the source code will be included in the device configuration. [. . . ]