User manual AMD AMD64 ARCHITECTURE

[. . . ] AMD64 Technology AMD64 Architecture Programmer's Manual Volume 1: Application Programming Publication No. 24592 Revision 3. 15 Date November 2009 AMD64 Technology 24592--Rev. 3. 15--November 2009 © 2002 ­ 2009 Advanced Micro Devices, Inc. The contents of this document are provided in connection with Advanced Micro Devices, Inc. [. . . ] 3. 15--November 2009 AMD64 Technology source operand from the third doubleword of the source operand and stores the result in the fourth doubleword of the destination. The HSUBPD instruction subtracts the second quadword of the destination register from the first quadword of the destination operand and stores the difference in the first quadword of the destination register. The difference from the subtraction of the first quadword of the source operand from the second quadword of the source operand is stored in the second quadword of the destination operand. Simultaneous Addition and Subtraction · ADDSUBPS--Add/Subtract Packed Single-Precision Floating-Point · ADDSUBPD--Add/Subtract Packed Double-Precision Floating-Point The ADDSUBPS instruction adds the second and fourth doublewords of the source operand to the second and fourth doublewords, respectively, of the destination operand and stores the resulting sums in the second and fourth doublewords of the destination operand; subtracts the first and third doublewords of the first operand from the first and third doublewords of the destination operand and stores the resulting differences in the first and third doublewords of the destination operand. The ADDSUBPD instruction subtracts the first quadword of the source operand from the first quadword of the destination operand and stores the difference in the first quadword of the destination operand; adds the second quadword of the source operand to the second quadword of the destination operand and stores the sum in the second quadword of the destination operand. Multiplication · MULPS--Multiply Packed Single-Precision Floating-Point · MULPD--Multiply Packed Double-Precision Floating-Point · MULSS--Multiply Scalar Single-Precision Floating-Point · MULSD--Multiply Scalar Double-Precision Floating-Point The MULPS instruction multiplies each of four single-precision floating-point values in the first operand by the corresponding single-precision floating-point value in the second operand and writes the result in the corresponding doubleword of the destination. The MULPD instruction performs an analogous operation for two double-precision floating-point values. The MULSS instruction multiplies the single-precision floating-point value in the low-order doubleword of the first operand by the single-precision floating-point value in the low-order doubleword of the second operand and writes the result in the low-order doubleword of the destination. The three high-order doublewords of the destination are not modified. The MULSD instruction multiplies the double-precision floating-point value in the low-order quadword of the first operand by the double-precision floating-point value in the low-order quadword of the second operand and writes the result in the low-order quadword of the destination. The highorder quadword of the destination is not modified. 128-Bit Media and Scientific Programming 169 AMD64 Technology 24592--Rev. 3. 15--November 2009 Division · DIVPS--Divide Packed Single-Precision Floating-Point · DIVPD--Divide Packed Double-Precision Floating-Point · DIVSS--Divide Scalar Single-Precision Floating-Point · DIVSD--Divide Scalar Double-Precision Floating-Point The DIVPS instruction divides each of the four single-precision floating-point values in the first operand by the corresponding single-precision floating-point value in the second operand and writes the result in the corresponding quadword of the destination. The DIVPD instruction performs an analogous operation for two double-precision floating-point values. For vectors of n number of elements, the operations are: operand1[i] = operand1[i] ÷ operand2[i] where: i = 0 to n ­ 1 The DIVSS instruction divides the single-precision floating-point value in the low-order doubleword of the first operand by the single-precision floating-point value in the low-order doubleword of the second operand and writes the result in the low-order doubleword of the destination. The three highorder doublewords of the destination are not modified. The DIVSD instruction divides the double-precision floating-point value in the low-order quadword of the first operand by the double-precision floating-point value in the low-order quadword of the second operand and writes the result in the low-order quadword of the destination. The high-order quadword of the destination is not modified. If accuracy requirements allow, convert floating-point division by a constant to a multiply by the reciprocal. Divisors that are powers of two and their reciprocals are exactly representable, and therefore do not cause an accuracy issue, except for the rare cases in which the reciprocal overflows or underflows. Square Root · SQRTPS--Square Root Packed Single-Precision Floating-Point · SQRTPD--Square Root Packed Double-Precision Floating-Point · SQRTSS--Square Root Scalar Single-Precision Floating-Point · SQRTSD--Square Root Scalar Double-Precision Floating-Point The SQRTPS instruction computes the square root of each of four single-precision floating-point values in the second operand (an XMM register or 128-bit memory location) and writes the result in the corresponding doubleword of the destination. The SQRTPD instruction performs an analogous operation for two double-precision floating-point values. The SQRTSS instruction computes the square root of the low-order single-precision floating-point value in the second operand (an XMM register or 32-bit memory location) and writes the result in the 170 128-Bit Media and Scientific Programming 24592--Rev. [. . . ] 174, 271 unpack instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141, 165, 213 UNPCKHPD instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 UNPCKHPS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 UNPCKLPD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ]