User manual ASUS P3P-1394

[. . . ] ® P3B-1394 IEEE-1394 Motherboard USER'S MANUAL USER'S NOTICE No part of this manual, including the products and software described in it, may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup purposes, without the express written permission of ASUSTeK COMPUTER INC. ASUS PROVIDES THIS MANUAL "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL ASUS, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR DATA, INTERRUPTION OF BUSINESS AND THE LIKE), EVEN IF ASUS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM ANY DEFECT OR ERROR IN THIS MANUAL OR PRODUCT. Product warranty or service will not be extended if: (1) the product is repaired, modified or altered, unless such repair, modification of alteration is authorized in writing by ASUS; or (2) the serial number of the product is defaced or missing. [. . . ] <F5> loads the last set values, <F6> and <F7> loads the BIOS default values and Setup default values, respectively. 4. BIOS SETUP Processor Serial Number (Disabled) The Processor Serial Number is a unique electronic number that is added to every Pentium III processor to help verify the identity of the user across the Internet. Set this field to Enabled when you need increased security for doing business online or e-commerce. Otherwise, set it to Disabled for greater anonymity when surfing the Internet. If you are not using a Pentium III processor on the motherboard, you may not make changes to this field. CPU Level 1 Cache / CPU Level 2 Cache (Enabled) These fields allow you to choose from the default of Enabled or choose Disabled to turn on or off the CPU's Level 1 and Level 2 built-in cache. CPU Level 2 Cache ECC Check (Disabled) This function controls the ECC check capability in the CPU level 2 cache. BIOS Update (Enabled) This functions as an update loader integrated into the BIOS to supply the processor with the required data. The BIOS will load the update on all processors during system bootup in the default position of Enabled. Quick Power On Self Test (Enabled) This field speeds up the Power-On Self Test (POST) routine by skipping memory retesting a second and third time. Setup default setting for this field is Enabled. A complete test of the system is done on each test. 4. BIOS SETUP BIOS Features 48 HDD Sequence SCSI/IDE First (IDE) When using both SCSI and IDE hard disk drives, IDE is always the boot disk using drive letter C (default setting of IDE). This new feature allows a SCSI hard disk drive to be the boot disk when set to SCSI. This allows multiple operating systems to be used on both IDE and SCSI drives or the primary operating system to boot using a SCSI hard disk drive. Boot Sequence (CDROM, A, C) This field determines where the system looks first for an operating system. Options are CDROM, A, C; D, A; E, A; F, A; C only; LS/ZIP, C; LAN, A, C; A, C; C, A; A, CDROM, C; and CDROM, C, A. The setup default setting is to check first the floppy disk and then the hard disk drive, that is, A, C. Boot Up Floppy Seek (Disabled) When enabled, the BIOS will seek drive A one time. Floppy Disk Access Control (R/W) This allows protection of files from the computer system to be copied to floppy disks by allowing the setting of Read Only to only allow reads from the floppy disk drive but not writes. The setup default R/W allows both reads and writes. ASUS P3B-1394 User's Manual 4. BIOS SETUP IDE HDD Block Mode Sectors (HDD MAX) This field enhances hard disk performance by making multi-sector transfers instead of one sector per transfer. [. . . ] The standard started from 10MBytes/sec to 160MBytes/sec available today. SDRAM (Synchronous DRAM) The SDRAM features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables the coexistence of high performance and a simple user interface. SDRAM takes memory access away from the CPU's control; internal registers in the chips accept the request, and let the CPU do something else while the data requested is assembled for the next time the CPU talks to the memory. As they work on their own clock cycle, the rest of the system can be clocked faster. [. . . ]