User manual ASUS P4B266-M

[. . . ] No part of this manual, including the products and software described in it, may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup purposes, without the express written permission of ASUSTeK COMPUTER INC. Product warranty or service will not be extended if: (1) the product is repaired, modified or altered, unless such repair, modification of alteration is authorized in writing by ASUS; or (2) the serial number of the product is defaced or missing. Products and corporate names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners' benefit, without intent to infringe. This device complies with FCC Rules Part 15. [. . . ] These fields allow you to choose from the default of [Enabled] or choose [Disabled] to turn on or off the CPU Level 1 and Level 2 built-in cache. This field functions as an update loader integrated into the BIOS to supply the processor with the required data. When set to [Enabled], the BIOS loads the update on all processors during system bootup. Otherwise, IRQ12 can be used for expansion cards. When you set this field to [Enabled], BIOS reserves IRQ12, whether or not a PS/2 mouse is detected at startup. When you set this field to [Disabled], the USB controller legacy mode is disabled whether or not you are using a USB device. When using OS/2 operating systems with installed DRAM of greater than 64MB, you need to set this option to [Enabled]. Otherwise, leave to the default setting [Disabled]. This parameter allows you to set the optimal timings for items 2­5, depending on the memory modules that you are using. The default setting is [By SPD], which configures items 2­5 by reading the contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module stores critical information about the module, such as memory type, size, speed, voltage interface, and module banks. This item controls the latency between the SDRAM read command and the time the data actually becomes available. The SDRAM CAS Latency parameter appears only when you set the SDRAM Configuration to [User Defined]. This item controls the latency between the SDRAM active command and the read/write command. The SDRAM RAS to CAS Delay parameter appears only when you set the SDRAM Configuration to [User Defined]. This item controls the idle clocks after issuing a precharge command to the SDRAM. The SDRAM RAS Precharge Delay parameter appears only when you set the SDRAM Configuration to [User Defined]. This item controls the number of SDRAM clocks used for SDRAM parameters. The SDRAM Active Precharge Delay parameter appears only when you set the SDRAM Configuration to [User Defined]. This feature allows you to select the size of mapped memory for AGP graphic data. When set to [4X Mode], this item allows 1066MB/s video data transfers through the AGP 4X interface card. When set to [1X Mode], the AGP interface only provides a peak data throughput of 266MB/s even if you are using an AGP 4X card. [. . . ] This is an industry-standard designation for memory capacity as a measure of the speed of the memory bus. New platform requirements ensure that memory does not become a bottleneck to system performance. PCI is a standard widely used by expansion card manufacturers. The PCI Bus Master can perform data transfer without local CPU help and furthermore, the CPU can be treated as one of the Bus Masters. [. . . ]