User manual BIOSTAR U8668-D

[. . . ] This equipment has been tested and found to c omply with the limits of a C lass B digital device, pursuant to Part 15 of the FCC Rules . t hese limits are designed to provide reasonable protection agains t harmful interference in a residential installation. This equipment generates , uses and can radiate radio frequency energy and, if not ins talled and used in accordance with the instructions, may c ause harmful interference to radio communications . There is no guarantee that interference will not occur in a partic ular installation. [. . . ] This submenu allows you to configure the specific features of the chipset installed on your system. This chipset manages bus speeds and access to system memory resources, such as DRAM and external cache. it also coordinates communications with the PCI bus. The default settings that came with your system have been optimized and therefore should not be changed unless you are suspicious that the settings have been changed incorrectly. If you highlight the literal "Press Enter" next to the "DRAM Clock" label and then press the enter key, it will take you a submenu with the following options: DRAM Clock This item determines DRAM clock following 100MHz, 133MHz or By SPD. SDRAM CAS Latency When DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Precharge to Active (Trp) This items allows you to specify the delay from precharge command to activate command. Active to CMD (Trcd) Use this item to specify the delay from the activation of a bank to the time that a read or write command is accepted. DRAM Command Rate This item controls clock cycle that must occur between the last valid write operation and the next command. If you highlight the literal "Press Enter" next to the "AGP & P2P Bridge Control" label and then press the enter key, it will take you a submenu with the following options: AGP Aperture Size Select the size of the Accelerated Graphics Port (AGP) aperture. Host cycles that hit the aperture range are forwarded to the AGP without any translation. This item occurs only as using onboard VGA. AGP Master 1 WS Write When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with one wait states. the Choices: Disabled (default) , Enabled. AGP Master 1 WS Read When Enabled, read to the AGP (Accelerated Graphics Port) are executed with one wait states. If you highlight the literal "Press Enter" next to the "CPU & PCI Bus Control" label and then press the enter key, it will take you a submenu with the following options: CPU to PCI Write Buffer When enabled, up to four Dwords of data. Can be written to the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU read cycle will not be completed until the PCI bus signals that it is ready to receive the data. When Enabled, writes to the PCI bus are executed with zero-wait states. the Choices: Enabled (default) , Disabled. PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. [. . . ] Some graphic controllers which are not VGA compatible take the output from a VGA controller and map it to their display as a way to provide boot information and VGA compatibility. However, the color information coming from the VGA controller is drawn from the palette table inside the VGA controller to generate the proper colors, and the Graphic controller needs to know what is in the palette of the VGA controller. to do this , the non-VGA graphic controller watches for the Write access to the VGA palette and registers the snoop data. In PCI based systems, where the VGA controller is on the PCI bus and a non-VGA graphic controller is on an ISA bus, the Write Access to the palette will not show up on the ISA bus if the PCI VGA controller responds to the Write. [. . . ]