User manual CADENCE DESIGN SYSTEMS CADENCE PALLADIUM XP TECH BRIEF

[. . . ] CAD E N C E PA L L A D I U M X P VERIFICATION COMPUTING PLATFORM TECHNICAL BRIEF Cadence® Palladium® XP is a state-of-the-art hardware/software verification computing platform. It unifies best-in-class simulation acceleration and emulation capabilities in a single environment to boost verification throughput and productivity. Its processor-based compute engine and Unified Xccelerator Emulator software runs highperformance verification applications and introduces flexible new use models that transcend traditional emulation. With unmatched scalability, advanced debug, hardware/software co-verification, and support for dynamic power analysis, hard and soft IP, and metricdriven verification, Palladium XP optimizes system design and verification. SYSTEM-LEVEL VERIFICATION CHALLENGE Traditional verification tools have not kept pace with the rapid rate at which system-on-chip (SoC) design size and complexity are growing. [. . . ] Palladium XP typically replaces the ASIC(s) being designed for the target system, enabling system-level and application software testing prior to silicon availability. Unlike other systems, Palladium XP supports both static and dynamic targets, so it interfaces easily with virtually any target environment. When interfacing with a real-world environment, it is sometimes necessary to control the relative timing of individual output signals from the emulator. Palladium XP provides direct support for all popular signal interfaces and has a vast number of I/O pins to support even the largest multi-user environments. Its UXE software can support HDL files encrypted by IP providers for protection, giving access only to the signals and registers permitted by that IP provider. Bonded-out microprocessor cores, silicon cores, or FPGA logic can be installed into the Palladium IP chassis using standard Cadence IP blocks, making it easy to utilize hard IP during verification. Palladium XP is fully compatible with the complete family of Cadence SpeedBridge Adapters, providing simple and direct integration with full-speed in-circuit verification environments. Each SpeedBridge product is a transparent speed/rate adapter that connects real-world systems with the design being emulated. Palladium XP can also take advantage of recent software enhancements for controlling various functions through the GUI, such as soft reset of the board and remote configuration. SpeedBridge Adapters are an option to Palladium XP. www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 7 USB Device PCI Express USB Host PCI/PCI-X SAS Interface to ThirdParty IP and Testers Palladium XP Verification Computing Platform SATA Wireless Video/ Audio MultiEthernet Multi-I/O Fibre Channel Figure 8: For most industry-standard protocols, off-the-shelf VIP such as SpeedBridge Adapters are available, enabling SoC designs running on Palladium XP to interface with real-world devices/targets/testers for system-level verification TRANSACTION-BASED ACCELERATION Transaction-based acceleration (TBA) is an optimized simulation acceleration mode that supports a transaction-oriented testbench modeling style. It accelerates logic simulation by several orders of magnitude. TBA uses message-level communication between the testbench components running on a workstation and the rest of the environment running on the Palladium XP platform. By using message-level communication rather than signal-level communication, TBA reduces the amount of communication overhead between the workstation and the emulator, thereby increasing overall acceleration performance. · Congruent TBA allows users to create a transaction-based environment without using the hardware. Using only a simulator, such as Incisive Enterprise Simulator, engineers can fully develop their models and optimize environment bring-up time. Once the models are fully functional, engineers can then migrate painlessly to hardware, where these same models will run unchanged yet faster than with standard simulation. With congruent TBA, results are guaranteed to be the same, regardless of which engine (Incisive or Palladium XP) is employed. · Concurrent TBA allows users to achieve near-emulation performance with designs being driven from a testbench. In this mode, the design runs continuously (free running) at full emulation speed while the testbench is running on the workstation. This unique feature is ideal for running large regression suites, where maximum performance is essential. Palladium XP employs an Accellera standardized interface--SCE-MI--and SystemVerilog DPI to simulators with support for standard and advanced testbench languages, including SystemVerilog, SystemC, and C/C++. www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 8 HYBRID ENVIRONMENT A hybrid of hardware and software verification IP (VIP) models can be used for increased predictability and productivity earlier in the design cycle. To complement TBA mode and further reduce design schedules, Cadence offers off-the-shelf VIP optimized for acceleration for various industry-standard protocols, as well as SpeedBridge Adapters optimized for emulation interfaces to various processor models, debuggers, and testers. [. . . ] By testing against various operational scenarios and "what-if" analysis to make architecture tradeoffs, designers can make better decisions to save power. SYSTEM-LEVEL POWER VERIFICATION To reduce static power, when part of the device or IP (power domain) is not being operated, it can be turned off using techniques such as power shutoff (PSO), which can drastically reduce SoC power consumption. But with the use of PSO and other power reduction techniques, power verification complexity increases. The challenge is to ensure that the design continues to function as designed. [. . . ]