User manual CADENCE DESIGN SYSTEMS CADENCE RF SIP METHODOLOGY KIT DATASHEET

[. . . ] CAD e N Ce r F S i P MeT H O D O LO G Y Ki T Over view The Cadence® rF SiP Methodology Kit accelerates the application of eDA technologies to system-in-package (SiP) designs for radio Frequency (rF) and wireless applications. it provides methodologies that maximize design productivity and predictability for customers leveraging the advantages of SiP technology. An integrated set of products built around proven methodologies enables complete front-to-back SiP design and implementation. [. . . ] By combining comprehensive links between system design, physical implementation and manufacturing, the kit allows full-SiP electrical analysis and characterization of critical paths as well as behavioral modeling from overall system-level simulation through bottom-up verification. These capabilities are demonstrated on a segment representative design (an 802. 11b/g wLAN rF SiP) that includes a Helic-based rF transceiver and analog baseband die in a 180nm generic CMOS process, a second AMS analog front-end baseband interface die in a 90nm generic CMOS process, and embedded and discrete passive off-chip components in a generic LTCC substrate. The kit also contains re-usable, pre-configured components from test-benches, models, and simulation plans for block and full SiP-level verification and physical implementation approaches. Additionally, design teams are led through a stepby-step example on how to apply advanced Cadence technologies to best achieve design success. A design team can use the segment representative design as a basis for understanding the methodology, and then map the demonstrated techniques and technologies to their own designs. This helps the team develop a realizable action plan to improve its own design process. The step-by-step approach further allows a team to absorb and understand a wide array of technologies that can optimize complex rF SiP designs. KIT COMPOSITION AND INTEGRATION THE CADENCE RF SIP METHODOLOGY KIT INCLUDES THE FOLLOWING NEW CADENCE SIP TECHNOLOGIES: · CadenceSiPRFArchitect Cadence SiP rF Architect provides the integration and flow environment linking the virtuoso® Analog Design environment (ADe) and Cadence SiP rF Layout. it enables the creation of a single simulation-capable top-level SiP rF Module schematic that includes the rF/analog iCs that are part of the final SiP design. it provides schematic-level prelayout definition and characterization of substrate-level embedded rF passive devices, as well as a bi-directional eCO and LvS flow between the substrate layout and the virtuoso ADe environment. rF/Analog iCs can be exported from the virtuoso Layout editor as design-ready SiP die footprints, including post-wafer-processing geometry adjustments. · CadenceSiPRFLayout Cadence SiP rF Layout comprises a physical detailed implementation environment for complete SiP rF substrate place and route. it includes final connectivity optimization, die stack creation, support for flipchip and wirebond attach die, rF embedded passive creation and optimization, manufacturing preparation, full design validation, and tapeout. · CadenceSiPDigitalSI Cadence SiP Digital Si fully integrates digital signal integrity (Si) analysis, interconnect extraction, and modeling with the physical SiP design environment. By combining proven Si technology in an environment that permits interactive editing of die-to-die and substrate interconnect, SiP design engineers can optimize a design to meet both electrical and physical requirements--while achieving reduced design cycle times. KEY BENEFITS · Combinessystemdesign, physicalimplementationand manufacturing in a complete, true iC/package co-design solution · Providesaseamlessflowstartingatfull-SiPelectrical simulation, through a single schematic-driven layout implementation and ends with comprehensive signal integrity checks · Achievesfunctional, performance, andclosed-loopverification across multiple technologies and design domains including system-level, digital, mixed-signal, and analog/rF · Improvessimulationaccuracyandcompletenessbyeffectively combining signal integrity analysis at SiP and parasitic extraction at iC-level · Optimizeson-andoff-chipconfigurationsbymanaging inductor synthesis and passive component modeling · Deliveredwithfivedaysofapplicabilityconsultingandexpert advice to help jumpstart and fine tune the rF SiP design process Applicability consulting SiP RF design flow pre- and post-layout simulation flow SiP LTCC generic process design kit RF verification suite test plans THE CADENCE RF SIP DESIGN METHODOLOGY KIT RELIES ON AND INTEGRATES WITH THE FOLLOWING VIRTUOSO TECHNOLOGIES (NOT INCLUDED): · VirtuosoSchematicEditor As the design composition environment for the virtuoso custom design platform, virtuoso Schematic editor delivers an extensive set of tools for custom iC design entry. From architectural definition using industry-standard language representations, such as verilog®, vHDL, and C, to final structural implementations at the transistor level, it aids in the implementation of each stage in a design. · Comprehensive flow documentation · RF SiP flow workshop · RF SiP whitepaper Cadence SiP Products Cadence SiP RF Architect Cadence SiP Digital SI Cadence SiP RF Layout Figure 1: Cadence RF SiP Methodology Kit www. ca de nce . com C A D eNC e C H i P O PTi Mi zer 2 · VirtuosoAnalogDesignEnvironment The virtuoso Analog Design environment is the analog design and simulation environment for the virtuoso custom design platform, and the industry's standard task-based environment for simulating and analyzing full-custom, analog, and rF iC designs. [. . . ] To help make tradeoffs between speed and accuracy, the vPCM synthesis module includes three different synthesis algorithms: quasi-static eM solution, full-wave eM solution, and scalable equivalent circuits. · VirtuosoXLLayoutEditor virtuoso XL Layout editor is the high-end custom block authoring physical layout tool in the virtuoso platform. it supports the physical implementation of custom digital, mixedsignal, and analog designs at the device, cell, and block levels. CADENCE SERVICES AND SUPPORT · Cadenceapplicationengineerscanansweryourtechnical questions by telephone, email, or internet--they can also provide technical assistance and custom training · Cadencecertifiedinstructorsteachover70coursesandbring their real-world experience into the classroom · Over25InternetLearningSeries(iLS)onlinecoursesallowyou the flexibility of training at your own computer via the internet · SourceLink® online customer support gives you answers to yourtechnicalquestions--24hoursaday, 7daysaweek-- including the latest in quarterly software rollups, product change release information, technical documentation, solutions, software updates, and more Formoreinformation contactCadencesalesat: 1. 800. 746. 6223 orlogonto: www. cadence. com ®2008CadenceDesignSystems, Inc. Allrightsreserved. Cadence, Assura, Spectre, SourceLink, Verilog, andVirtuosoareregisteredtrademarksandthe CadencelogoisatrademarkofCadenceDesignSystems, Inc. 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