User manual CADENCE DESIGN SYSTEMS ENCOUNTER CONFORMAL CONSTRAINT DESIGNER DATASHEET

[. . . ] Encounter Conformal Constraint Designer is available in L and XL configurations. Cadence® Encounter® Conformal® Constraint Designer, a key component of the Cadence Logic Design Team Solution, automates the validation, generation, and refinement of SDC timing constraints. By ensuring that timing constraints are valid throughout the entire design process, and by pinpointing real design issues early, quickly, and accurately, Encounter Conformal Constraint Designer helps designers achieve rapid timing closure with fewer iterations, leading to more predictable schedules. · Improvesqualityandprovidesearly predictability of silicon in terms of area, timing, and power by using higher quality constraints · Reducesriskofre-spinsthroughformal validation of exception constraints · Speedsconvergencefortimingclosure by quickly validating failing timing paths as functionally false · Increasesvisibilityandconfidenceversus original intent, as the design constraints transform · Helpsuserscreateinitialconstraints effortlessly with the SDC Template Generator and false-path generation capability directly from RTL hierarchical constraint checking, while also checking for the overlaps among constraints. In addition, Conformal Constraint Designer generates false-path exceptions through functional path analysis and provides an extensive debugging and analysis environment to pinpoint the errors in SDC and arrive at correct constraints quickly. SDC QUALITY CHECKS Conformal Constraint Designer ensures functionally correct SDC specifications in a design context by checking different aspects of specification and design: · Checkswithdesignelements;for example, reference points are not connected in a multi-chip package · EnforcesSDCsyntaxandadditional requirements · Flagssyntacticallylegalbutproblematic constructs, such as incorrect mode setup BENEFITS · Shortensdesigncyclesbycheckingthe creation and integration of block-level and top-level constraints FEATURES Conformal Constraint Designer automates SDC validation by checking SDC for structural, syntax, and implementation issues and then functionally verifying the exception constraints. [. . . ] Implementation and STA tools may have inconsistent precedence rules or select pessimistic constraints, which result in poor quality of silicon. Designers must have an opportunity to review the conflicts and decide on the proper course of action. Conformal Constraint Designer reports duplicated or overwritten constraints and overlapping exceptions, so designers can accomplish this task efficiently and formally. HIERARCHICAL CONSTRAINT CHECKS Block designers typically write SDC independently from top-level constraints. When chip integrators or physical designers assemble the chip, they may find that the constraints have conflicts in terms of clock definition, set I/O delay settings, and exceptions. Conformal Constraint Designer can quickly and easily detect these errors early in the design cycle with hierarchical constraint checks. It checks the SDC of the design at different hierarchical levels--chip-level SDC vs. block-level SDC--and pinpoints conflicts, overlap, or other issues related to clocks, SDC COMPARE Duringthedesignprocess, optimization tools may transform reference objects in the design. Also, as a design progresses, users may add to or change SDC files. The impact of adding or deleting timing constraintscanbeobserved;forexample, the impact of adding a timing exception upon the rest of the design. It can check before-and-after, or can be used Figure 2: For an invalid false path exception, Encounter Conformal Constraint Designer can show the path of concern and a waveform that triggers it www. cadence. com ENCOUNTER CONFORMAL CONSTRAINT DESIGNER 2 SDC INTEGRATION Given a set of block-level constraints, Conformal Constraint Designer can generate the top-level constraints through the use of default or user-defined precedence rules, easing the process of assembling the design for placeand-route. FALSE-PATH GENERATION FROM RTL Conformal Constraint Designer can generate meaningful false-path statements directly from the RTL, which accelerates timing closure. As with timing report validation, these new exceptions are the product of formal validation. Figure 3: Clock Domain Crossing checks as viewed in helix extensible platform CLOCK DOMAIN CROSSINGS Clocks are defined within SDC constraint files. Checking for structural issues with clock domain crossings (CDC) is a perfect task for Conformal Constraint Designer while the quality and consistency of timing constraints is checked. The false paths can also be found in asynchronous behavior of designs, and analysis and validation of these paths are performed accordingly. Statements that simply cover too many paths can also be flagged. A counter-example is generated when validation fails, quickly pinpointing the active path and the waveform that enables it. TIMING REPORT VALIDATION Designers can spend enormous amounts of time debugging timing reports to separate functional false paths from true ones. Conformal Constraint Designer automates and accelerates this validation process by identifying false paths from critical timing reports and generating new SDC exceptions. These results can be used to improve synthesis, place-and-route, or STA results. [. . . ] LSF is supported. CADENCE SERVICES AND SUPPORT · Cadenceapplicationengineerscan answer your technical questions by telephone, email, or Internet--they can also provide technical assistance and custom training · Cadencecertifiedinstructorsteach morethan70coursesandbring their real-world experience into the classroom · Morethan25InternetLearningSeries (iLS) online courses allow you the flexibility of training at your own computer via the Internet ·CadenceOnlineSupportgivesyou 24x7onlineaccesstoaknowledgebase of the latest solutions, technical documentation, software downloads, and more CONFIGURATIONS Conformal Constraint Designer is available in L and XL configurations, and with an XL Option. The L configuration offers · Validation - SDC check - Hierarchical checks - FPvalidation · Generation - Timing report generation The XL configuration offers · Validation - SDC check - Hierarchical checks - FPvalidation - MCPvalidation · Generation - Timing report generation - Template generation - SDC Advisor - SDC integration - FPgeneration The XL Option offers · SDCCompare · Multi-modeconstraints INTEGRATION WITH THE ENCOUNTER PLATFORM Conformal Constraint Designer can be run standalone or as part of the Encounter Digital Implementation System, Encounter RTL Compiler, and Encounter Timing System. SDC quality and hierarchical checks can be invoked from the synthesis (quality only), place-and-route, and STA environments, displaying any constraint conflicts or inconsistencies. [. . . ]