User manual CADENCE DESIGN SYSTEMS ENCOUNTER CONFORMAL ECO DESIGNER DATASHEET

[. . . ] ENC O U N T E R C O N F O R M A L ECO D E S I G N E R DATASHEET ENCOUNTER CONFORMAL TECHNOLOGY To shorten overall design-cycle times and minimize silicon re-spins, designers need production-proven validation. Encounter Conformal verification technologies offer the most comprehensive solutions for equivalence checking, design constraint management, functional ECO analysis and generation, and low-power design verification. Cadence® Encounter® Conformal® ECO Designer enables designers to implement RTL engineering change orders (ECOs) for pre- and post-mask layout. It combines automatic ECO analysis and design netlist modification with world-class equivalence checking to provide superior performance, productivity, capacity, and ease-of-use. management recognize ECOs as a time of high stress, long work hours, and uncertainty. [. . . ] It combines proven equivalence checking and functional checks, and uses formal techniques to analyze and implement the functional ECO. Encounter Conformal ECO Designer is available in two configurations: an XL package, which targets primarily the pre-mask ECO flow; and a GXL package, which additionally targets the post-mask ECO flow using metal-only layers and spare gates. ENGINEERING CHANGE ORDERS Engineering change orders (ECOs) have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. A logical change to a design netlist is referred to as functional ECO while all other changes are classified as non-functional. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. Engineering and RTL Logic Equivalence Checking Old Gate/DEF New RTL w/ECO Extended Functional Checks Clock Domain Crossing Checks Semantic Checks Structural Checks Equivalence Checking Support for Complex Datapath Logic Synthesis (Area, Power, Timing, Yield) Datapath and Test Synthesis Floorplanning and Physical Synthesis ECOs Encounter Conformal ECO Designer Automatic ECO Analysis and Design Netlist Modification Place and Route Physically-Aware Spare Gate Mapping for Post-Mask ECO Encounter Conformal ECO Designer Modified Gate Netlist Final Layout Encounter Conformal ECO Designer GXL Figure 1: Encounter Conformal ECO Designer offers automatic ECO analysis and design netlist modification BENEFITS · Providesfasterturnaroundtimeby minimizing manual intervention and eliminating time-consuming iterations · Generatesearlyestimateson ECO feasibility · Provideshighvalueinthedesigncycle when schedule delays are highly visible · Improvesdesignerproductivityand offers flexibility to do ECO with metal-only layers, thus reducing manufacturing costs · Reducesverificationtimesignificantly by verifying multimillion-gate designs much faster than traditional gate-level simulation · Decreasestheriskofmissingcritical bugs through independent verification technology FEATURES Encounter Conformal ECO Designer combines logic equivalence checking (for the most complex SoC and datapath-intensive designs) with functional ECO analysis, design netlist modification, clock domain synchronization, and semantics checks. Figure 2, the original netlist (G1) is compared against the new netlist (G2) to determine what has changed. Equivalence checking is also used at the tail end of the process to make sure the ECO implementation was successful both for front-end and back-end signoff. EQUIVALENCE CHECKING FOR ECO During development, a design undergoes numerous iterations prior to final layout, and each step in this process has the potential to introduce logical bugs. Encounter Conformal ECO Designer checks the functional equivalence of different versions of a design at these various stages and enables designers to identify and correct errors as soon as they are introduced. Equivalence checking also plays an important role in the ECO implementation process. It helps the ECO analysis tool identify which modules and logic cones in the design require change to implement the ECO. For instance in FUNCTIONAL ECO ANALYSIS Encounter Conformal ECO Designer has a built-in ECO analysis engine that can identify the differences between the original design netlist (G1) and the new design netlist (G2). Users can perform ECO analysis on the entire design or on specific modules within the design hierarchy, which is typically more efficient. Once the ECO analysis step is completed and the logic change optimized, Encounter Conformal ECO Designer performs the necessary netlist modifications to achieve the new function in the original design netlist (G1). Alternately, Encounter Conformal www. cadence. com ENCOUNTER CONFORMAL ECO DESIGNER 2 New RTL (R2) Old RTL (R1) Design netlist (G3) is the hand-off point to the back-end physical implementation tool targeting a pre-mask or post-mask flow. Tool features: · Supports combinational and sequential (the addition of new state elements) changes of the design · Supports the addition of new ports · Preserves the clock trees · Preserves the scan chain · Preservers the original netlist structure (G1) when it creates the new ECO netlist (G3) · Recycles freed-up cells during the ECO analysis process Synthesis Synthesis Test Insertion Place & Route SoC Encounter System New Netlist (G2) Old Netlist (G1) Old DEF Incremental Optimizations P&R Encounter Conformal ECO Designer ECO Netlist (G3) Final Netlist Figure 2: The Encounter Conformal ECO Designer implementation flow ECO Designer can write out an ECO script that can be used to make direct changes to the place-and-route database. INTEGRATED ENVIRONMENT An intuitive graphical user interface (GUI) is provided for setup and debugging, allowing the user to work more productively and quickly pinpoint the cause of equivalence mismatches. [. . . ] In tandem, `analyze www. cadence. com ENCOUNTER CONFORMAL ECO DESIGNER 3 For more information contact Cadence sales at: +1. 408. 943. 1234 or log on to: www. cadence. com/ contact_us © 2009 Cadence Design Systems, Inc. Cadence, Conformal, Encounter, and Verilog are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. [. . . ]