User manual CADENCE DESIGN SYSTEMS ENCOUNTER CONFORMAL LOW POWER DATASHEET

[. . . ] ENC O U N T E R C O N F O R M A L LOW P O W E R Figure 1: Encounter digital IC design platform Encounter platform products are available in L, XL, and GXL offerings. G0001 DATASHEET ENCOUNTER PLATFORM To release innovative products in narrow market windows, companies need to focus precious engineering resources on where they add the most value-- differentiating their designs. The Cadence Encounter digital IC design platform offers a full spectrum of technologies for nanometer-scale SoC design, helping both Logic Design and physical implementation teams achieve high-quality silicon quickly. As an integrated RTL-to-GDSII design environment, the Encounter platform provides a complete flow--from RTL synthesis and test design, through silicon virtual prototyping and partitioning, to final timing and manufacturing closure. [. . . ] Semantic checks connect low-power cells--level shifters, Optimizing for leakage and dynamic power Place and route Structural checks isolation, and state retention registers--into helps designers reduce energy use and Encounter Conformal Low Power is Clock domain crossing check an RTL design, thus enabling true low lower cooling and packaging costs. While available in XL and GXL offerings. Physical synthesis power RTL to gate equivalence checking. advanced low power methods--such The tool can also model level shifters and as static and dynamic voltage/frequency BENEFITS isolation cells as domain anchor points scaling, power gating, and state Encounter ECOs during equivalence checkingEC Ldetect retention--offer additional power savings, · Minimizes silicon re-spin risk by providing Conformal to whether logic gates have erroneously they also complicate the verification task. complete verification coverage crossed domain boundaries from one Final layout low power implementation · Detects version of the netlist to another. errors early in the design cycle Extends equivalence Datapath synthesis checking to datapath and layout vs. schematic (LVS) reference SPICE netlist E N C O U N T E R CONFORMAL LOW POWER w w w. c a d e n ce. com Conformal EC XL Encounter Custom circuit design Figure 4: Encounter Conformal Low Power debug Environment Figure 3: Illustrates power domain highlighting capability in Encounter Conformal Low Power XL STRUCTURAL AND FUNCTIONAL CHECkING FOR LOW POWER DESIGN Encounter Conformal Low Power XL supports multi-supply voltage island (MSV), coarse grain power gating (PSO), and coarse grain ground switching (GSO), dynamic voltage and frequency scaling (DVFS), and state retention power gating design techniques. It also makes it possible to perform power domain structural and functional checks on an RTL design with CPF, a logical gate netlist (typically postsynthesis), and a power aware physical gate netlist (post-place and route). For RTL and logical gate netlist checking using a non-CPF based implementation flow, the user manually defines, using Encounter Conformal commands, the power domains, ground domains, voltages, standby conditions, power modes, and power associations, along with the lowpower cells being used. For a CPF-based implementation flow, the tool derives all the setup information directly from CPF. The software then propagates domains throughout the design hierarchy and identifies all domain boundary crossings. Finally, it reports: · Power and ground domain assignment related problems and floating connections · Level shifter: Missing, redundant, wrong domain location, or wrong connectivity · Isolation cell: Missing, redundant, wrong gate type, or wrong location, wrong isolation enable polarity · Control signals that are not powered appropriately Encounter Conformal Low Power XL supports dedicated and non-dedicated isolation cells, as well as combination isolation and level shifter cells. It also performs isolation and state retention functional checks using formal methods. [. . . ] It can also help validate that the isolation cells used in the low power design are appropriate. For more information Email us at icinfo@cadence. com or visit www. cadence. com. Cadence Design Systems, Inc. Corporate Headquarters 2655 Seely Avenue San Jose, CA 95134 United States 800. 746. 6223 +408. 943. 1234 (outside U. S. ) www. cadence. com © 2007 Cadence Design Systems, Inc. Cadence, Conformal, Encounter, and Verilog are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. [. . . ]