User manual CADENCE DESIGN SYSTEMS ENCOUNTER DFT ARCHITECT DATASHEET

[. . . ] ENCOUNTER DFT ARCHITECT DATASHEET Creating a complete manufacturing test (silicon verification) methodology has typically required post-netlist use of separate software products. This is an inefficient and often error-prone approach that results in lower quality, lower productivity, and higher product manufacturing costs. Encounter DFT Architect is a key component of a single true "global" synthesis environment where logic and DFT constructs are compiled in a single pass for concurrent optimization across multiple parameters, including timing, area, and power. [. . . ] Using global synthesis and the Common Synthesis Designer Power Format (CPF), DFT with DFT Verification Architect creates, inserts, hierarNetlist Signoff chically connects, and verifies all IC test structures for a design Advanced Physical based on user specification. The Verification result is faster development of a higher-quality function and IC test Physical ATPG Implementation infrastructure at lower cost of development and silicon verification. Silicon Figure 3: Encounter digital IC design platform www. cadence. com ENCOUNTER DFT ARCHITECT 2 BENEFITS · Concurrentlogic+DFTsynthesisacross area, timing, and power parameters · GreaterproductivityfromRTLtoATPG by moving test decisions, structure verification, and analysis to the front-end flow (see Figure 2 below) · Accelerateddevelopmentofahigher quality IC test infrastructure · Power-AwareDFTtotestfunctionmode low power techniques, including clock gating, Multi-Supply Multi-Voltage (MSMV), MTCMOS (e. g. course grain) and Power Shut-off (PSO) · Power-AwareATPGforwithEarly Power Estimation (EPS) capabilities to identify power issues during test mode and reduce or eliminate costly iterations and respins to achieve power closure · AutomaticICtestinfrastructure insertion and verification from a single specification and environment · Enableshierarchicalandflatdesign flows · Eliminateserrorsfrommanualstitching and integration · TestCoverageOptimizationearly testability analysis through TPI · FullyintegratedMBISTsolution optimizes memory test development time and reduces project cost · Flexiblecompressionarchitectures-- including MISR, XOR, or hybrid-dramatically reduce manufacturing test cost, increase throughput, and optimize diagnostic flows. · Advancedmaskingarchitectures ensure the highest compression while maintaining full-scan coverage. A Single True-Synthesis Environment with Advanced ATPG DRC Checks Minimize Design Iterations Problem: · ATPG DRC run after synthesis. · Each violation requires a design change and rerun synthesis. Solution: · Add ATPG checks to Synthesis Environment · Enable identification and autofix capability to these problems early in flow - 3-state contention check on internal and external nets - Async set-reset race condition - Clock and data race condition - Floating nets - X-source checking Figure 4: Automation through integration ·Userenvironmentwithapowerful schematic browser gives the designer control over what is displayed, how the circuit is displayed, how far tracing will go, and hierarchical navigation. A block can have its output nets traced, justified, and sensitized manually for easy debug and analysis ·Flexible, highlyautomatedmethodology for inserting all top-level I/O and test structures, including IEEE 1149. 1/6 boundary scan controller, I/O test, and support for additional custom functions or variations ·ScaninsertionwithEncounterRTL Compiler "global" synthesis technology. Required hierarchical connections to the TAP controller are addressed at the top level. Designers can also use any industry-standard macro or IP for block-level scan insertion ·Physically-awarescanplacementand ordering capability. ·Fullsuiteofultra-fastchecking, auto-repair, and analysis functions-including test structure verification, boundary scan conformance checking, and verification­allows cores to be isolated for SoC testing. Interactive analysis capabilities include a powerful schematic browser with simulation and fault analysis capabilities ENCOUNTER DFT ARCHITECT ADVANCED DFT Architect Advanced includes all of the features of Encounter Architect Basic, plus XOR and MISR compression and MBIST capabilities. DFT Architect Advanced compiles and connects compression structures, and its capabilities are enhanced by tight links to Encounter True-Time ATPG Advanced technology. True-Time ATPG Advanced works with the inserted compression structures to cut test costs and reduce scan test time and data volume [by as much as or greater than 100X] DFT Architect Advanced offers a highly flexible approach to compression that allows implementation of a multiple input signature register (MISR) architecture with the highest compression ratio, and an exclusive-or (XOR)­based architecture that enables a highly efficient compression ratio and a one-pass diagnostics methodology ·On-productMISRplus(OPMISR+) includes input fanout, broadcasting each scan pin to multiple scan-chain inputs, and MISR-based output compression, which eliminates the need to check the response at each cycle FEATURES ENCOUNTER DFT ARCHITECT BASIC DFT Architect Basic includes all of the features required to create the basic test infrastructure for digital designs, including: www. cadence. com ENCOUNTER DFT ARCHITECT 3 ·XOR-basedcompressionincludes input fanout with the addition of an XOR-based spreading network, and XOR-tree­based output compression, which enables a one-pass diagnostics methodology ·Flexible, yetcomprehensivemasking algorithms for OPMISR and XOR compression strategies that maintain full-scan fault coverage and the most efficient pattern and tester cycle count (e. g. , wide0, wide1 masking). TAP-controlled, serialized compression meets or exceeds the lowest pin count requirements DFT Architect Advanced also enables Power-aware Test, including Power-aware DFT, Power-aware ATPG and Power-aware Analysis. Power-aware DFT supports low power designs implementing a Power Shut-Off (PSO) structure with the insertion of specialized test structures such as Power Test Access Mechanism (PTAM) that ensure stability of power domains during manufacturing test and provides an ability of setting up different power mode for test. The automatic creation of test modes for each of these power modes, allows for verification of low power intent and generation of power safe patterns at the tester. Information from the Common Power Format (CPF) is taken to compile and connect all low power DFT structures into complete full-chip low power DFT infrastructure. [. . . ] In addition, the Encounter True-Time ATPG product has intelligent ATPG algorithms which minimize scan correlation issues, delivering demonstrated results of >99. 5 stuck-at test coverage with >100x test-time reduction. Optional X-state masking capability is available on a per-chain per-cycle basis. Masking is usually required when using delay test because delay ATPG may generate unknown states in the circuit. [. . . ]