User manual CADENCE DESIGN SYSTEMS ENCOUNTER DIGITAL IMPLEMENTATION SYSTEM DATASHEET

[. . . ] It extends the production-proven Encounter technologies that designers trust to deliver truly scalable, ultraefficient core memory architecture and end-to-end multi-core parallel processing for the ultimate in capacity and performance. A comprehensive solution for mainstream and advanced node flat and hierarchical designs, it addresses the requirements for design closure, signoff, low power, mixed signal, and manufacturability and yield optimization. and analysis using black blobs and automated floorplan synthesis, clock tree and clock mesh synthesis, advanced nanometer routing, mixed-signal support, advanced low-power implementation, and a complete suite of design-formanufacturability, variation, and yield optimization technologies required for advanced node designs. These and other capabilities enable Encounter Digital Implementation System to deliver the highest quality of silicon for timing, signal integrity, area, power, and yield, including integrated statistical-based analyses and optimizations. [. . . ] Finally, NanoRoute superthreading technology combines the best of multi-threading, multi-core, and parallel-processing techniques. This enables designers to route millions of nets per hour on both readily available and cost-effective 32-bit compute technologies and the latest developments in multi-core processing hardware. Digital Implementation System supports register retiming, accurate physical layout prediction, multi-supply voltage (MSV)-aware synthesis, and other features to achieve high quality of silicon (QoS). Its integrated and physically-aware synthesis technology enables designers to dramatically improve gate-level netlists derived from other synthesis tools, resulting in superior timing, area, and power. The integrated signoff solution enables: · Industry-endorsedandsilicon-proven timing, noise, and power analysis during implementation and signoff · Consistentsignoffanalysesand extraction between implementation in Encounter Digital Implementation System and signoff in Encounter Timing and Power Systems, as well as QRC extraction, for faster design convergence · Multi-dimensionalroot-causeanalysis for power and timing that shaves weeks off of tapeout schedules and prevents silicon failures · Fastestturnaroundtimeforincremental or ECO extraction with built-in integrated QRC extraction · Theindustry'smostpreciseSIanalysis for reduced crosstalk noise margins · High-throughput, multi-coreparallel processing architecture with truly concurrent multi-mode/multi-corner analysis · Earlyrailanalysisandpower-switch optimization leveraging Encounter Power System for highly optimized, correct-by-construction power network design · Staticanddynamicpowerrailanalysis with IR-drop and clock-jitter impact on timing · Variation-aware, statisticaltiming and leakage power analysis with effective current source model support for greater accuracy at advanced process nodes CONCURRENT CHIP/PACKAGE DESIGN: FLIP-CHIP SUPPORT Encounter Digital Implementation System flip-chip floorplanning and implementation technologies enable the concurrent design of chip and package by including package constraints and parasitic effects while designing the IC. With support for multiple I/O methodologies, concurrent optimization of area and peripheral I/Os with core instances, automatic RDL routing with 45-degree support, and accounting for RDL layers during signal/power routing, Encounter Digital Implementation System eliminates the traditional manual steps in I/O placement and optimization. This mature technology has been proven through multiple customer tapeouts. ADVANCED GLOBAL DEBUG AND DIAGNOSTICS Debug and diagnosis challenges often come late in the design cycle, along the critical path toward reaching final tapeout. Encounter Digital Implementation System timing, power, and clock debug and diagnostics capabilities provide significant advantage by enabling designers to quickly zero in on and visualize interdependent timing, clock, and power issues, then quickly resolve them using powerful "what-if" analysis techniques--with results that can be immediately implemented in physical design. SIGNOFF ANALYSIS Successful digital chip design hinges on accurate and consistent signoff analysis. By integrating with Encounter Power System, Encounter Timing System, and Cadence QRC Extraction, Encounter Digital Implementation System addresses logical, physical, electrical, and manufacturing domain requirements in a single, easy-to-use environment. This enables convergent front-end to back-end design handoff, signoff-driven implementation, and highly accurate final chip signoff that analyzes chip timing, signal integrity (SI), power consumption, statistical static timing, electromigration, and thermal characteristics. ADVANCED RTL SYNTHESIS RTL synthesis for high-performance systems requires not only high capacity but also advanced features to optimize the design. Encounter www. cadence. com ENCOUNTER DIGITAL IMPLEMENTATION SYSTEM 3 ADVANCED NODE DESIGN ADVANCED PROCESS VARIATION SUPPORT Variations in manufacturing can result in structural changes in devices and interconnect, leading to deviations in their electrical behavior. Key design-for-yield (DFY) features include wire-spreading, wire-widening, double-cut via insertion, single via reduction and optimization, critical area analysis and optimization, true lithography distortion prevention and optimization, CMP-aware metal fill, and a rich set of random and systematic visual analysis and text-based reporting vehicles. Encounter Digital Implementation System's robust native DFY capabilities allow designers to quickly and accurately predict manufacturing variability and to make intelligent tradeoffs during prototyping and implementation for maximizing yield. flow that follows the core principles of prevention, optimization, analysis, and signoff to deliver "correct by design" results. LOW-POWER DESIGN Design teams constantly strive to reduce power consumption at the chip or systems level to become and remain competitive in today's industry. However, power must be considered with other design goals in a simultaneous and multi-objective optimization approach. Encounter Digital Implementation System is an integral part of the Cadence Low-Power Solution, which provides a complete design-tosignoff methodology. It begins with early design planning and system architecture then continues through front-end design, functional verification, synthesis, physical implementation, packaging, and signoff. Encounter Digital Implementation System's underlying infrastructure simplifies the implementation of low-power designs because it is multiple power domain­aware across the flow. Floorplanning, placement, clock tree synthesis, optimization, routing, analysis, and all other steps in the design flow comprehend and optimize across all power domains simultaneously. The native integration of complete multisupply voltage (MSV) management also enables automatic placement of level shifters with all power connections completed automatically. This enables the implementation of designs that employ power reduction techniques such as power shutoff (PSO), MSV, dynamic voltage/frequency scaling (DVFS), substrate biasing, and many more. [. . . ] Engineering change orders (ECOs) can be managed more easily since they no longer require the generation of LEF/DEF/GDSII files to communicate the changes. Comprehensive full-chip static timing analysis has always been challenging for mixed-signal designs, typically because the custom/analog design engineers had to manually create Liberty (. lib) files for their completed mixed-signal blocks. Encounter Digital Implementation System has a unique ability to perform comprehensive static timing analysis by transcending the analog hierarchy and extracting the digital logic and paths. The Cadence Mixed-Signal Solution combines all of the strengths of Encounter Digital Implementation System, including design closure, signoff analysis, advanced node design, and low-power design with the industry-standard Virtuoso design platform for custom/analog design, enabling a mixed-signal implementation solution that is second to none. CADENCE SERVICES AND SUPPORT · Cadenceapplicationengineerscan answer your technical questions by telephone, email, or Internet--they can also provide technical assistance and custom training · Cadencecertifiedinstructorsteach more than 70 courses and bring their real-world experience into the classroom · Morethan25InternetLearningSeries (iLS) online courses allow you the flexibility of training at your own computer via the Internet ·CadenceOnlineSupportgivesyou 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more PLATFORMS · lnx86:Linux(x86andx86_64)32/64bit · sol86:Solaris(x86_64)64bit · sun4v:Solaris(ultraSparc)64bit · ibmrs:AIX(power)64bit For more information contact Cadence sales at: +1. 408. 943. 1234 or log on to: www. cadence. com/ contact_us © 2010 Cadence Design Systems, Inc. [. . . ]