User manual CADENCE DESIGN SYSTEMS ENCOUNTER TIMING SYSTEM DATASHEET

[. . . ] Global timing debug employs unique path visualization capabilities to determine a path's cause of failure. Paths that share a common failure mode can then be categorized dynamically while the debugging of "uncategorized" paths continues. Path categories can be visualized in the global timing context to determine which FEATURES Encounter Timing System provides a comprehensive signoff verification solution that combines STA, accurate delay calculation, crosstalk noise analysis, advanced modeling, and global timing debug. It helps designers achieve first-pass silicon success and fast time to market on their multimillion-gate designs. [. . . ] Encounter Timing System provides power analysis by employing both vectored and vectorless approaches. The vectorless approach allows accurate power analysis early in the design flow, while vectors are used to achieve the highest accuracy. 25 ETS XL Propagated No Propagation Figure 4: SI pessimism reduction and critical path simulation ACCURATE CROSSTALK ANALYSIS AND FASTER SI CLOSURE Encounter Timing System calculates the impact of crosstalk using a combination of cell- and transistor-level models. For noisy nets that exhibit the most non-linear behavior, Encounter Timing System uses an on-the-fly SPICE simulation engine to calculate noise-on-delay effects accurately. It also deploys the unique path-basedalignment(PBA)techniqueto ensure realistic SI delay effects on critical timingpaths. WithoutPBA, SIdelay calculation can create an unrealistic or overly pessimistic worst-case path delay. Further removal of path delay pessimism is achieved through noise path pessimism removal (NPPR), which finds the maximum noise delay change for the overall critical path instead of for each individual net on that path. (See Figure 4. ) Encounter Timing System also ensures functional validity by performing glitch noise propagation to register end points and by ensuring that the register is not drivenunstable. TheseuniquePBA, NPPR, and glitch noise propagation capabilities greatly reduce the number of false crosstalk problems. This translates into much less work for place-and-route systems and a dramatically reduced number of SI closure iterations. AUTOMATED MULTI-MODE MULTICORNER SIGNOFF AND ECO Encounter Timing System's unique Multi-Mode Multi-Corner (MMMC) infrastructure enables designers to quickly analyze and debug timing problems across all modes and corners. It features www. cadence. com # of Violations 499k 1 29 39. 5k 8 49 2. 7M 18 496 810k 1 272 184k 1 5 1. 3M 14 31 682k LOW-POWER­DRIVEN SIGNOFF In smaller geometries, power supplies are typically around 1 volt, and even small voltage drops can compromise signal timing and lead to chip failures. IR drop further increases the risk of crosstalk failure. Encounter Timing System accurately models the non-linear IR drop impact and eliminates the inaccuracies of the traditional linear K-factor approach. The system incorporates instance-based IR drop data from Cadence VoltageStorm® Power Verification to account for the effects of static and dynamic IR drop on path delays and SI. Advanced low-power techniques such as multi-supply/multi-voltage (MSMV) and dynamic voltage and frequency scaling (DVFS) can introduce errors and complicate the traditional timing signoff flow. Encounter Timing System enables a simple flow where designers cancharacterizejustthreelibrariesat three voltage points, which are sufficient to perform accurate non-linear delay calculation across a much wider range of voltage points. Encounter Timing System also supports the Common Power Format (CPF), which describes the power intent throughout the design flow from system specification to tapeout. 4400 a unique concurrent MMMC analysis with distributed and threaded processing capability that provides simplified management of MMMC runs coupled with the highest possible throughput. This is complemented by the MMMC-aware incremental ECO capability which allows users to make an ECO and see the effect on timing and across all modes in a single session, without running additional reports or scripts. MULTI-PROCESSING ARCHITECTURE Encounter Timing System utilizes both threaded and distributed processing to greatly improve overall signoff turnaround. Through threaded timing and SI analysis, users can expect to gain up to four times the performance over a single CPU run. This corner-based approach can be overly pessimistic since it reports timing scenarios that have an extremely small likelihood of occurring. Also, the exponential growth in the number of corner combinations with the increasing number of parameters makes analysis on every corner impractical. Encounter Timing System supplements traditional corner-based methods with powerful and accurate statistical static timing analysis (SSTA) that can account for the process variability in a single run. (See Figure 5. ) It uses advanced statistical ECSM models to identify cells and nets on both clock and data paths that are sensitive to variations; and determines the probability of timing failure over the full range of process variation. [. . . ] Existing leakage power analysis techniques use a pessimistic worst-case leakage that has a very small likelihood of occurring in real silicon. Since cell leakage has an exponential response to process variation (that is, a small change in processvariationcausesamajorshift in transistor leakage), the probability distribution becomes skewed such that the extreme worst case has a very small chance of occurring. (See Figure 6. ) This situation leads to aggressive over-design, over-compensation for IR drop, and potentially unnecessary architectural changes. The solution is to model the leakage power as a statistical probability to avoid designing to the worst-case limit. [. . . ]