User manual CADENCE DESIGN SYSTEMS LITHO ELECTRICAL ANALYZER DATASHEET

[. . . ] CADEnCE LITHO ELECTRICAL AnALyzER DATASHEET CadenCe Litho eLeCtriCaL anaLyzer Cadence Litho Electrical Analyzer allows designers using sub-90nm processes to identify and analyze parametric issues associated with manufacturing variability and to minimize their effect on chip performance--all within their existing flows for IP, custom analog, and cellbased digital design. Cadence Litho Electrical Analyzer uses fab-certified technology to predict contours across the process window and to predict device and interconnect silicon electrical behavior. [. . . ] Cell-based chip designers simply input their DEF, SPEF, library information, and fab DFM technology files directly into Litho Electrical Analyzer. It is fast enough to quickly iterate with place-and-route: designers tighten their design margins, run place-and-route, and then use Litho Electrical Analyzer to identify hotspots and produce optimization directives. Features VariaBiLity-aware eLeCtriCaL design In sub-90nm design, systematic variations are the greatest cause of chip failures, causing electrical issues such as timing, signal integrity, and leakage power. At 65nm, systematic variations of 3nm on a transistor gate can cause a 20% variation in delay and double the impact on leakage power. With traditional corner-based design methodologies, margins are applied everywhere regardless of context. This over-design with excessive guardbanding stalls timing closure and can still result in unexpected parametric failures due to unforeseen systematic manufacturing variations. Over-designing to avoid DFM issues also results in penalties to both area and leakage power. For custom design, Litho Electrical Analyzer takes in a SPICE netlist and SPICE models to predict current density across channels, extracting device parameters for transistors from the embedded Cadence Litho Physical Analyzer model-based silicon contour predictions. Silicon-proven device modeling of contour-based (nonrectangular) transistor gates takes into account the short channel effect of a MOSFET inside the device channel to extract the proper device parameters. It then produces a backannotated transistor SPICE netlist. It also applies the changes in RC data to the designer's existing DSPF or SPEF file to represent the true effects of in-context silicon shape variations, without creating new nodes or parasitic elements. Designers can then simulate the backannotated netlist with their SPICE simulator to check the effect of variations on their design and detect potential failures before going to silicon. Litho Electrical Analyzer integrates with Cadence QRC Extraction in a flow that extracts transistor parameters from contours and writes out a transistor-level netlist in SPICE or DSPF formats or as an extracted view. For place-and-route designs, Litho Electrical Analyzer also calculates the change in delay and timing skew based on the in-context shape variations, and it provides delay variations back to static timing analysis tools in the form of an incremental SDF. [. . . ] Cadence, encounter, spectre, and Virtuoso are registered trademarks and the Cadence logo is a trademark of Cadence design systems, inc. all others are properties of their respective holders. [. . . ]