User manual CADENCE DESIGN SYSTEMS NANOROUTE ADVANCED DIGITAL ROUTER DATASHEET

[. . . ] NAN O R O U T E A D VA N C E D DIG I TA L R O U T E R DATASHEET NANOROUTE ADVANCED DIGITAL ROUTER Nanometer-scale designs today require a new generation of physics-, electrical-, and manufacturing-aware routing technology. [. . . ] Integrated with Cadence Encounter® Digital Implementation System and available as a standalone router, NanoRoute Router ensures top-quality silicon and high performance for large systems-on-chip and application-specific designs. RTL Physical synthesis Physical prototype placement LEF/DEF SDC/. lib NanoRoute Router Noise Timing SDF DEF/GDSII Figure 1: NanoRoute Advanced Digital Router is integrated with Encounter Digital Implementation System, but is also available as a standalone product grid-based router with off-grid flexibility, and it concurrently evaluates and optimizes interconnect topology based on 3D effects on timing, area, power, manufacturability, and yield. Powered by a superthreading backplane (either multi-thread or distributed processing), the NanoRoute solution finishes millions of nets of connectivity per hour. It delivers the highest quality of results in a fraction of the time taken by other routers on the market. CAPABILITIES SMART ROUTING NanoRoute Router's new generation of SMART technology (SMART2) holistically and simultaneously evaluates and optimizes the interdependent objectives of signal integrity, manufacturing awareness, routing, and timing. SMART2 technology features: · Fullsupportofprocessdesignrules (both restricted and recommended) from 130nm to 32/28nm and smaller · Designformanufacturability(DFM)such as via and interconnect optimization · Automatedpreventionandfixingfor lithography effects · Shieldingsupportandsignalintegrity 3D coupling effect reduction · Largecapacityandhighutilization support · Dynamicmulti-CPUsupportwith superthreading technology In traditional approaches to routing, issues of coupling effect, power, area, and especially DFM are addressed sequentially and mutually exclusive from one another. BENEFITS · Enablestheimplementationoflarge, complex designs on advanced or mainstream process technologies - Mitigates process variation by supporting a wide range of advanced node processes - Improves overall quality of results, maximizes utilization, and meets multiple design objectives - Shrinks die size by 5-10% with robust routing technology and congestion handling results - Offers higher capacity for larger, more complex designs · Enhancesproductivitythroughefficient single-CPU and multi-CPU performance - Delivers 10x or more performance gain - Speeds turnaround time with dynamic multi-thread and distributed processing capability · Ensuresaconvergentpathtodesign tapeout and production silicon - Offers a silicon-proven track record with successful customer tapeouts and foundry endorsements This approach is inadequate for today's designs. For example, signal integrity and power are isolated from process variation and should not be optimized separately from manufacturability. Otherwise, a fix for one requirement will likely introduce a change for the other and create new conflicts. The same is true for routability and manufacturing awareness. The plethora of new foundry-enforced manufacturing requirements and yield enhancement guidelines can significantly alter the RC characteristics and crosscoupling dynamics of the design, and changes to either must be aware of both timing and signal integrity. [. . . ] Cadence, the Cadence logo, Encounter, and NanoRoute are registered trademarks of Cadence Design Systems, Inc. [. . . ]