User manual CADENCE DESIGN SYSTEMS SIP DIGITAL DESIGN DATASHEET

[. . . ] However, this also means it requires expert engineering talent in widely divergent fields, which, to date, has limited mainstream adoption. By streamlining the integration of multiple high-pin-count chips onto a single substrate through a concurrent connectivity driven co-design methodology, the Cadence SiP digital co-design technology allows companies to adopt what were once expert engineering SiP design capabilities for mainstream product development. Cadence SiP solutions seamlessly integrate into Cadence Encounter ® technology for die abstract co-design, Cadence Virtuoso® technology for RF module design, and Cadence Allegro® technology for package/ board co-design. (See Figure 1. ) A COMPLETE CONNECTIVITY DRIVEN CO-DESIGN SOLUTION The Cadence digital-driven SiP flow focuses on the design challenges of integrating multiple large high-pin-count chips onto a single substrate. [. . . ] To model and simulatecomplex3DSiPstructures, SiP Digital SI integrated S-Parameter support, and fast, high-capacity simulation (10, 000 bits in seconds) to provide a unique combination of fast and accurate multigigahertz interconnect analysis. BENEFITS · Providesahighlyintegratedphysical and electrical design and simulation environment · Pre-postrouteinterconnectanalysiswith graphical topology exploration enables rapid what-if performance tuning · IncludesaSPICE-basedsimulation engine and embedded integration with athird-partysupplied3Dfieldsolver · Enablesrapidevaluationofcostversus performance tradeoffs through its virtual prototyping environment · Reads/writesCadenceDigitalSiP Layout files · Ensuressufficientandefficientpower delivery network (PDN) design www. ca de nce . com C A D ENC E SiP D I G I TAL DESI G N 3 KEY FEATURES* *Reference the product capabilities grid at the end of this datasheet to see what features are applicable to what product. to build the physical SiP implementation. The SiP architect can then use the graphical, intuitive editing tools to construct and evaluate critical sections of the design. (See Figure 5. ) SYSTEM CONNECTIVITY MANAGER The System Connectivity Manager is the "cockpit" or "dashboard" of the SiP Digital Architect. It allows the project architect to rapidly author and/or capture the connectivity of the SiP, which includes importing IC die Verilog netlists for chips that comprise the SiP design and interfacing to the PCB footprint symbol of the completed SiP. Embedded LVS routines and ECO management capabilities ensure that the logical SiP definition matches the physical SiP implementation, including any ICs that are partitioned and co-designed as part of the SiP. (See Figure 2. ) Figure 3: Virtual System Interconnect Models I/O PLANNER The IC die abstract I/O planner provides the definition and optimization of codesign die bump matrix, I/O pad ring/array through connectivity assignment, I/O placement, and redistribution layer (RDL) routing. It can create either a die abstract from scratch, or load an abstract from the digital IC design team (LEF/DEF or OA), and then optimize it in the context of the SiP substrate as well as other IC die in the design. The I/O planner is based on Encounter technology, ensuring it is 100 percent compatible with the chip design team's IC tools and provides complete IC technology file compliance. (See Figure 4. ) Figure 5: Substrate Floorplanner 3D DIE STACK EDITOR Thediestackeditorprovidesa3D construction environment for assembling complex die stacks which can include spacers, interposers and die attach methods such as wirebond and flip chip. (See Figure 6. ) Figure 2: System Connectivity Manager VIRTUAL SYSTEM INTERCONNECT (VSIC) MODELS An integrated graphical and topological interconnect modeling and simulation capability provides the ability to create and explore the signal integrity (SI) performance of proposed system-level connectivity. Embedded simulation capability provides time and frequency domain interconnect simulation, including industry-standard S-Parameter models. The embedded integration with a thirdpartysuppliedfull3Dquasi-staticfield solver further provides the extraction and creation of detailed, accurate geometric IBIS, RLGC or S-Parameter models of complex3Dinterconnectstructures. (See Figure 3. ) Figure 6: 3D Die Stack Editor 3D DESIGN VIEWER TheCadence3DDesignViewerisafull, solidmodel3Dviewerand3Dwirebond DRC solution for complex IC package designs. It allows users to visualize and investigate an entire design, or a selected design subset, such as a die stack or complex via array. It also provides a common reference point for cross-team design reviews. (See Figure 7. ) Figure 4: I/O Planner SUBSTRATE FLOORPLANNER The floorplanner allows the physical prototyping and evaluation of various substrate-level SiP implementation concepts. It provides a full rules-driven, connectivity-based capability that ensures a correct-by-construction approach. The die abstracts, discrete components, and connectivity and constraint data is used www. ca de nce . com C A D ENC E SiP D I G I TAL DESI G N 4 Figure 8: Integrated Constraint Management Figure 7: 3D Design Viewer INTEGRATED CONSTRAINT MANAGEMENT The spreadsheet based Integrated constraint management system provides the definition, application, and management of interconnect constraints and topologies at the physical prototyping and implementation level. [. . . ] An included Kulicke & Soffa verified loop profile library ensures that any wirebond patterns designed meet manufacturing signoff. Wirebond attached die flags and power/ground rings can be quickly created, edited, and optimized for multiple voltage supplies. (See Figure 13. ) Figure 12: Comprehensive ARC checking environment Figure 13: Auto/Interactive wirebonding using Kulicke & Soffa verified wire profiles www. ca de nce . com C A D ENC E SiP D I G I TAL DESI G N 6 PRODUCT FEATURES SiP DIGITAL ARCHITECT GXL SiP DIGITAL ARCHITECT XL SiP DIGITAL LAYOUT GXL SiP DIGITAL SI XL SiP RF ARCHITECT XL · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · i/a only · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · SiP RF LAYOUT GXL FRONT-END DESIGN CREATION FEATURES Virtuoso Analog Design Environment, schematic/layout integration and flow Substrate-level embedded RF passive synthesis System Connectivity Manager with logical co-design objects Full SiP LVS (substrate and ICs) Parasitic back annotation into system-level test benches SIGNAL INTEGRITY FEATURES SigXplorer topology editor and simulator (pre-route capabilities) SigXplorer topology editor and simulator (pre- and post-route capabilities) S-Parameter interconnect modeling and SI simulation Source synch and serial interface simulation 3DPCBfull-packagesimulationmodelcreation Embeddedintegrationwitha(third-partysupplied)3Dfieldsolver Co-planar coupling extraction Spectre transistor-level simulation engine Channel analysis for high-capacity SI simulation Power Delivery Network (PDN) optimization and verification Etch back stub effects simulation Package/pin delay length report SUBSTRATE DESIGN FEATURES Constraint Manager (electrical/physical and DRC) Import/export APD (. mcm) database Interactive (i/a) and automatic component (packaged and bare die) placement i/a only Auto/interactive wirebonding including rapid autobond User-definable wirebond model profiles including XML import Full and partial design connectivity assignment and optimization (router-based, closest match, interactive and constraint-based) Interactive and automatic interconnect routing (free angle and multi-layer orthogonal) On-line soldermask checking Recursive breakout pattern creator (flip-chip and wirebond) Static-style screen rulers ADVANCED DESIGN FEATURES I/O planning co-design editor (using LEF/DEF and OA 2. 2) Hierarchical GDSII output Team-based design (Design partitioning) Embedded RF passive creation and editing 3DDesignViewerand3DwirebondDRC 3DDieStackEditor Interconnect cline spreading BGA editor Constraint-driven HDI design DFM PREPARATION/OUTPUT Die/BGA footprint compare using DEF/OA/. TXT Filled shapes (metal) creation and editing Design documentation (dimensioning, annotation) Assembly Rule Checking (ARC) system Etch back of plating traces Plating bar generation Manufacturing/documentation export/import capabilities (stream, dxf, AIF) Substrate mask output (Gerber, GDSII) Full design-status reporting capabilities Waived DRCs (creation and reporting) Degassing of filled metal shapes Thieving (metal area balancing) www. ca de nce . com C A D ENC E SiP D I G I TAL DESI G N 7 SPECIFICATIONS SYSTEM REQUIREMENTS · OpenGLgraphicscompliancewith a minimum 64MB of dedicated graphics memory CADENCE SERVICES AND SUPPORT · Cadenceapplicationengineerscan answer your technical questions by telephone, email, or Internet--they can also provide technical assistance and custom training · Cadencecertifiedinstructorsteach morethan70coursesandbring their real-world experience into the classroom · Morethan25InternetLearningSeries (iLS) online courses allow you the flexibility of training at your own computer via the Internet · SourceLink® online customer support gives you answers to your technical questions--24hoursaday, 7daysa week--including the latest in quarterly software rollups, product change release information, technical documentation, solutions, software updates, and more PLATFORM/OS · WindowsXP, VistaEnterprise · Solaris · Linux INTERFACES · LEF/DEF5. 1to5. 7 · OA2. 2 · Verilog THIRD-PARTY SUPPORT · Apache-DAembeddedPakSI-E3D field solver engine For more information, contact Cadence sales at: 1. 800. 746. 6223 or log on to: www. cadence. com/ cadence/contact_us © 2008 Cadence Design Systems, Inc. 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