User manual CADENCE DESIGN SYSTEMS SIP RF DESIGN DATASHEET

[. . . ] In addition to lowering cost, reducing power consumption, and increasing performance, SiP design offers the flexibility to mix RF and high-speed digital circuitry in the same package. However, these advances require expert engineering talent in widely divergent fields--and conventional solutions have failed to automate the design processes required for efficient SiP development. By enabling and integrating design concept exploration, capture, construction, optimization, and validation of complex multi-chip and discrete substrate assemblies on printed circuit boards (PCBs), Cadence SiP design technology streamlines the process of combining multiple high-pin-count chips on a single substrate. This approach allows companies to adopt the most advanced SiP design capabilities for mainstream product development. Cadence SiP design technology integrates seamlessly with Cadence Encounter® technology for die abstract co-design, Cadence Virtuoso® technology for RF module design, and Cadence Allegro® technology for package/board co-design. [. . . ] It supports all packaging methods including PGA, BGA, micro-BGA, chip scale, flipchip, andwirebondattach. SiPRFLayout GXLisbasedonaco-designprocessthat manages physical, electrical, and manufacturing interfaces between design components--across all associated design fabrics--allowing designers to make tradeoffs and optimize the entire system interconnect. Full online and batch design-rule checking (DRC) supports the complex and unique requirements of all combinations of laminate, ceramic, and deposited substrate technologies. SiP RF LayoutGXLalsosupportsmultiplecavities, complex shapes, and interactive and automatic wirebonding. BENEFITS · Providesbi-directionalECOandLVS flow between RF design team and SiP RF module layout team · Supportssubstrate-levelRFpassive P-cell creation through Virtuoso top-level driven design · AllowsdirectimportofSiPsubstrateready IC die footprints from Virtuoso LayoutEditor · Speedsdiestackassemblyandoptimization with 3D creation/editing · OptimizesICI/Opadring/arrayco-design and connectivity at IC, substrate, and system levels · MinimizeslayerusagebyoptimizingSI and routability-driven connectivity assignment between ICs and substrate · Reducestedious, time-consuming manual breakout editing via flip-chip die autoroute-breakout · Constraint-drivenHDIdesignwith automation-assisted interactive routing enables greater design miniaturization, speeds implementation, and reduces potential errors · IncludescomprehensivesubstrateDFM capabilities for rapid design manufacturing preparation · IncludestheCadence3DDesignViewer and DRC for accurate, full 3D wire bondability verification, design review debug, and design documentation for assembly and test www. ca de nce . com C A D ENC E Si P RF D ESI G N 3 C A DENCE SiPDIGITALS I Cadence SiP Digital SI provides an environment for the co-simulation of SiP interconnect including embedded ICs and the target PCB. By using its integrated SI, parasitic extraction, and embedded integration with third-party 3D field solvers, engineers can make tradeoffs to minimize cost while maximizing performance of the package module interconnect. To model and simulate complex 3D SiP structures, SiP Digital SI includes embedded integration with third-party 3D field solvers, integrated S-Parameter support, and fast, high-capacity simulation (10, 000 bits in seconds) to provide a unique combination of fast and accurate multi-gigahertz interconnect analysis. ·Ensuressufficientandefficientpower delivery network (PDN) design · IncludesaSPICE-basedsimulation engine and embedded integration with a third-party supplied 3D field solver · Createsfullorpartialinterconnect3D parasitic models for backannotation into Virtuoso testbenches · Quicklyevaluatescostversusperformance tradeoffs through its virtual prototyping environment BENEFITS · Providesahighlyintegratedphysical and electrical design environment · Enablesrapidwhat-ifperformance tuning via pre- and post-route interconnect analysis with graphical topology exploration KEYFEATURES* *Referencetheproductcapabilitiesgrid at the end of this datasheet to see what features are applicable to what product. I/O PLANNER (FOR DIGITAL IC DIE CO-DESIGN) The IC die abstract I/O planner defines and optimizes co-design die bump matrixes, I/O padring/array through connectivity assignment, I/O placement, and redistributionlayer(RDL)routing. Itcaneither create a die abstract from scratch or load an abstract from the digital IC design team(LEF/DEForOpenAccess), andthen Figure 3: Flow integration between Virtuoso software and SiP RF Layout GXL FLOW INTEGRATION BETWEEN VIRTUOSO LAYOUT EDITOR AND SiP RF LAYOUT GXL SiPRFArchitectXLprovidesasingle integrated design flow built around the Virtuoso DFII framework. It also provides a single, system-level, simulation-ready Virtuoso schematic for RF/analog die, SiP substrate, and packaged and embedded passive components. It enables direct export of SiP-level IC die footprints from VirtuosoLayoutEditorandschematicdriven SiP substrate-level RF P-cell creation. For post-route circuit simulation, SiP RF ArchitectXLprovidesacompleteparasitic extraction (including use of Virtuoso RF Designer for inductors) and backannotation methodology including automatically maintained circuit simulation testbenches for critical signal paths. (See Figure 3. ) Figure 4: Integrated Constraint Management INTEGRATED CONSTRAINT MANAGEMENT The spreadsheet-based integrated constraint management system defines, applies, and manages interconnect constraints and topologies at the physical prototyping and implementation level. Designers can import constraints and apply them to industry-standard bus protocols such as PCI Express and DDR2/ DDR3 through hierarchical interconnect topology templates available from Cadence as well as various IC vendors. (See Figure 4. ) Figure 5: I/O planner www. ca de nce . com C A D ENC E Si P RF D ESI G N 4 optimize it in the context of the SiP substrate as well as other IC die in the design. The I/O planner is based on proven Encounter technology ensuring it is 100% compatible and compliant with the IC design teams technology file. (See Figure 5. ) SUBSTRATE EDITOR The substrate place-and-route editor allows the package layout designer to physically implement the SiP design based on the final chosen concept. It provides a full rules-driven, connectivity-based capability(drivenbySiPRFArchitectXL's integration with the Virtuoso environment) for top-level SiP netlist definition, ensuring a correct-by-construction approach. The die abstracts, discrete components, and connectivity and constraint data are used to implement the physical SiP. Substrate-level passive structures (inductors, capacitors, transmission lines, etc. ) defined during connectivity capture and circuit simulation are synthesized into physical metal structures as intelligent programmable cells. The package layout designer can then use the graphical, intuitive editing tools to implement the design and prepare it for manufacturing. [. . . ] Engineers can quickly check tradeoffs to the physical design to ensure that electrical requirements are not compromised. Extracted parasitic models can be backannotated into the top-level Virtuoso SiP schematic and testbenches for post-route circuit simulation. www. ca de nce . com C A D ENC E Si P RF D ESI G N 6 PACKAGE MODELING FOR SYSTEM-LEVEL ANALYSIS CreationofIBIS, RLC, orCadenceDML interconnect models is easily accomplished, either for a selected set of nets or for the entire package. Design teams can then easily re-use these models at the system level to ensure that package effects are properly considered when optimizing PCB cost/performance tradeoffs. INTEGRATION WITH CHIP-LEVEL IR DROP ANALYSIS Creation of package power and ground RLCmodelsthatcanbeautomatically consumed by IC core IR drop analysis (static and dynamic) is accomplished using Cadence VoltageStorm® power analysis. (See Figure 12. ) Figure 12: Integration with VoltageStorm for chip-level IR drop analysis including the package VIRTUOSO COMPATIBILITY · 5. xforCDBAand6. 1. 1forOA · Productandflowtrainingtofityour needs and preferred learning style ­ Over 80 instructor-led courses-- certified instructors, real world experience ­ Morethan25InternetLearning Series(iLS)onlinecourses · Cadencecustomersupportthatkeeps your design team productive ­ Cadence applications engineers provide technical assistance ­ SourceLink® online support gives you access to software updates, technical documentation, and more--24 hours a day, seven days a week SPECIFICATIONS SYSTEM REQUIREMENTS · OpenGLgraphicscompliancewith a minimum of 64MB of dedicated memory THIRD-PARTY SUPPORT · AgilentRFDE(ADSandMoMentum) for pre- and post-layout extraction and simulation · EmbeddedPakSI-E3Dfieldsolver engine from Apache-DA PLATFORM/OS · WindowsXP, VistaEnterprise · Solaris · Linux CADENCE SERVICES AND SUPPORT · Customer-focusedsolutionsthat increase ROI, reduce risk, and achieve your design goals faster ­ Collaborative approach and design infrastructure--virtual teaming ­ Proven methodology and flow tuned to your design environment ­ Design and EDA implementation expertise INTERFACES · LEF/DEF5. 1to5. 7 · OA2. 2 · Verilog® language For more information, contact Cadence sales at: 1. 800. 746. 6223 or log on to: www. cadence. com/ cadence/contact_us www. ca de nce . com C A D ENC E Si P RF D ESI G N 7 PRODUCT FEATURES SiPDIGITAL ARCHITECT GXL SiPDIGITAL ARCHITECT XL SiPDIGITAL LAYOUT GXL SiP DIGITAL SIXL SiP RF ARCHITECT XL · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · i/a only · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · SiP RF LAYOUT GXL FRONT-END DESIGN CREATION FEATURES Virtuoso Analog Design Environment, schematic/layout integration and flow Substrate-level embedded RF passive synthesis System Connectivity Manager with logical co-design objects FullSiPLVS(substrateandICs) Parasitic back annotation into system-level test benches SIGNAL INTEGRITY FEATURES SigXplorertopologyeditorandsimulator(pre-routecapabilities) SigXplorertopologyeditorandsimulator(pre-andpost-routecapabilities) S-Parameter interconnect modeling and SI simulation Source synch and serial interface simulation 3D PCB full-package simulation model creation Embedded integration with a (third-party supplied) 3D field solver Co-planar coupling extraction Spectre transistor-level simulation engine Channel analysis for high-capacity SI simulation Power Delivery Network (PDN) optimization & verification Etch back stub effects simulation Package/pin delay length report SUBSTRATE DESIGN FEATURES Constraint Manager (electrical/physical and DRC) Import/export APD (. mcm) database Interactive (i/a) and automatic component (packaged and bare die) placement i/a only Auto/interactive wirebonding including rapid autobond User-definablewirebondmodelprofilesincludingXMLimport Full and partial design connectivity assignment and optimization (router-based, closest match, interactive and constraint-based) Interactive and automatic interconnect routing (free angle and multi-layer orthogonal) On-line soldermask checking Recursive breakout pattern creator (flip-chip and wirebond) Static-style screen rulers ADVANCED DESIGN FEATURES I/Oplanningco-designeditor(usingLEF/DEFandOA2. 2) Hierarchical GDSII output Team-based design (Design partitioning) Embedded RF passive creation and editing 3D Design Viewer and 3D wirebond DRC 3D Die Stack Editor Interconnect cline spreading BGA editor Constraint-driven HDI design DFM PREPARATION/OUTPUT Die/BGAfootprintcompareusingDEF/OA/. TXT Filled shapes (metal) creation and editing Design documentation (dimensioning, annotation) Assembly Rule Checking (ARC) system Etch back of plating traces Plating bar generation Manufacturing/documentation export/import capabilities (stream, dxf, AIF) Substrate mask output (Gerber, GDSII) Full design-status reporting capabilities Waived DRCs (creation and reporting) Degassing of filled metal shapes Thieving (metal area balancing) www. ca de nce . com C A D ENC E Si P RF D ESI G N 8 © 2008 Cadence Design Systems, Inc. [. . . ]