User manual CADENCE DESIGN SYSTEMS SOC ENCOUNTER RTL-TO-GDSII SYSTEM DATASHEET

[. . . ] SOC ENCOUNTER RTL-TO-GDSII SYSTEM DATASHEET SOC ENCOUNTER RTL-TO-GDSII SYSTEM The SoC Encounter System combines RTL synthesis, silicon virtual prototyping, design planning, and full-chip digital implementation in a single system, and has been enhanced to support today's high-performance advanced node designs. Engineers can synthesize, physically implement, and optimize a flat virtual prototype--with the benefit of actual routed interconnect--giving designers an early, accurate view of design feasibility. Once feasibility is established, designers can immediately progress to full-scale implementation without ever having to leave the environment. [. . . ] These features enable designers to quickly generate prototype floorplans. Add to this the built-in flexibility and editing capabilities such as relative floorplanning--specifying relationships for pre-routes, resizable objects, multiple relations, datapath stacking, and integrated analysis tools--and the designers are now able to quickly and accurately reach an optimal final floorplan. Additionally, the floorplan ranking system helps designers to automatically generate multiple floorplan scenarios in parallel and analyze them based on predefined quality-of-results (QoR) criteria to explore as much of the physical solution space as possible and to enable the most informed assessment of design feasibility. timing optimization), litho-aware routing, and the industry's only superthreading technology, Cadence NanoRoute Router is unmatched in quality and performance for block-level and top-level routing, while simultaneously meeting multiple design objectives for the ultimate DRC-clean tapeout-ready GDSII database. ® The NanoRoute Router further extends its leading gridded and graph-based routing and optimization technologies to include space-based technologies and support for the latest 65- and 45-nanometer design rules. Space-based route optimization becomes especially important in the presence of design-for-yield requirements, where having the flexibility to go beyond the routing grid can provide significant yield improvements not achievable in any other system. Finally, NanoRoute routing features superthreading--which combines the best of both multithreading and parallel-processing techniques--to deliver the power to route millions of nets per hour on readily available and inexpensive 32-bit computer farms. ADVANCED RTL SYNTHESIS RTL synthesis for high-performance systems requires not only high capacity but also advanced features to optimize the design. The SoC Encounter System supports register retiming, accurate physical layout prediction, multi-supply voltage (MSV)­aware synthesis, and other features to achieve high quality of silicon. In addition, high capacity has been given special emphasis through multithreading support. ADVANCED PROCESS VARIATION SUPPORT Variations in manufacturing can result in structural changes in devices and interconnect, leading to deviations in their electrical behavior. At 65 nanometers and below, process control becomes significantly more challenging, leading to a larger variation as a percentage of the total size of the design's features. As a result, designs that pass traditional signoff standards could still fail in silicon due to process variations. In addition to providing foundry-supported signoff technologies for timing, SI, and power during implementation, the SoC Encounter System further extends these technologies by employing location-based on-chip variation (LOCV), which uses logic level and physical location to select the optimal de-rating factor. LOCV eliminates the excessive guardbanding associated with traditional de-rating and improves timing closure. ADVANCED DESIGN CLOSURE The global physical synthesis capability of the SoC Encounter System optimizes multiple paths simultaneously while performing multi-dimensional and concurrent optimization for timing, signal integrity (SI), power, area, congestion, and wire length and yield, using native signoff engines in the process. Additionally, significant improvements in performance, accuracy, and throughput can be achieved using robust MMMC analysis and optimization technologies. AUTOMATIC FLOORPLAN SYNTHESIS AND RANKING Today's physical design teams are expected to start physical implementation and design planning very early in the design cycle--with early and multiple versions of the design netlist--to determine design feasibility. Among the questions needing answers are the following: Can the design be NANOMETER ROUTING With its patented architecture and fast concurrent S. M. A. R. T. routing technology (unified signal integrity, manufacturing-aware, routability, and www. cadence. com S oC ENCOUNTER R TL-TO-GDSII SYSTEM 2 SoC Encounter technology also supplements traditional single- and multicorner­based methods with powerful and accurate statistical static timing analysis (SSTA) that accurately accounts for variability of process parameters in a single run. Using advanced statistical ECSM models, the SoC Encounter System identifies cells and nets on both clock and data paths that are sensitive to variations, and determines the probability of timing failures over the full scope of the process window. This reduces pessimism and allows for less guardbanding, which decreases area and power consumption while improving chip performance. [. . . ] The challenges often come late in the design cycle, along the critical path for reaching final tapeout. SoC Encounter debug and diagnostics capabilities provide significant advantage by enabling designers to quickly zero in on and visualize interdependent timing, clock, and power issues, then quickly resolve them using powerful "what-if" analysis techniques--with results that can be immediately implemented in physical design. MIXED-SIGNAL DESIGN Today's high-performance designs have a high percentage of analog components, and the SoC Encounter System handles these mixed-signal designs efficiently without abstracting the information. It also provides interfaces to custom implementation and routing tools and technologies. LOW-POWER DESIGN Advanced low-power techniques such as power gating (MTCMOS) and dynamic voltage and frequency scaling (DVFS) use multiple power domains. [. . . ]