User manual CADENCE DESIGN SYSTEMS VIRTUOSO DIGITAL IMPLEMENTATION DATASHEET

[. . . ] VIR T U O S O D I G I TA L IMP L E M E N TAT I O N DATASHEET VIRTUOSO DIGITAL IMPLEMENTATION Designed to complement Cadence® Virtuoso® Layout Suite, Virtuoso Digital Implementation enables capacitylimited* execution of the complete digital implementation solution from RTL-toGDSII. [. . . ] Both technologies are based on the industry-leading Encounter digital IC design platform, proven to produce high quality of silicon (Figure 1). *Virtuoso Digital Implementation enables an RTL-to-GDSII solution that is limited in capacity. Encounter RTL Compiler synthesis is limited to a final mapped instance count of 50k instances or 200k generic instances. Encounter Digital Implementation is limited to a capacity of 50k instances. Cadence® Virtuoso® Digital Implementation is a complete synthesis and place-and-route system. It enables small digital block implementation in the context of an advanced analogdriven methodology for mixed-signal designs. Virtuoso Digital Implementation automates synthesis and optimizes place-and-route, accelerating the mixed-signal design process and ensuring the highest quality of silicon. VIRTUOSO PLATFORM Virtuoso Spec-driven Environment Virtuoso Spectre Circuit Simulator Virtuoso UltraSim Full-chip Simulator Virtuoso XL Layout Editor Virtuoso Chip Assembly Router Assura Physical Verification LEF/DEF OpenAccess ENCOUNTER PLATFORM Encounter RTL Compiler SoC Encounter L · Encounter digital implementation · 2-layer to n-layer · Cost effective Figure 1: Virtuoso Digital Implementation Two Virtuoso Digital Implementation licenses can be combined ("stacked") to double the capacity limits. For users who require larger or unlimited capacity, other Encounter products are available. BENEFITS · Enablesautomateddigital implementation for small digital blocks, including synthesis and physical implementation · Matchesthefunctionalityenabledby the Encounter Digital Implementation L product · Ensuresthebestqualityofsiliconfor digital logic (speed, area, and power) · CombineswiththeVirtuosoplatformto enable a complete physical implementation solution for mixedsignal designs* · Providesextremelyfastturnaroundtime in achieving design closure · EnablesCadenceFirstEncounter® silicon virtual prototyping · Built-inphysicaloptimizationenables rapid timing closure · Timing-drivenimplementation supported by a common timing engine enabled with a signoff quality delay calculator · Integratespowerplanning, power routing and power analysis · Multiplepowerdomainsupport · Easy-to-useclocktreesynthesishandles multiple and re-convergent clocks · Includesclock-gatingforlowpower design · SeamlesslysupportsSDC · Supportslibrariesandrulesofmultiple process technologies down to 28nm · Supportsrectilinearblocks · LEF/DEFdatatransferviastandard interfaces and OpenAccess** * Requires Virtuoso Layout Suite XL or Virtuoso Layout Suite GXL products ** The loading/display/data handling of custom objects-- including pCells, RODs, multi-part paths and fig groups--is enabled using the Encounter Mixed Signal GXL Option, which must be purchased separately. FEATURES RTL SYNTHESIS · Read/writestandardinputs/outputs · Built-inhigh-performancedatapath · Arithmeticoptimizations · Totalnegativeslack(TNS)optimization · Testabilityanalysisandscaninsertion · Clockgating · Multi-Vtleakagepoweroptimization CLOCK TREE SYNTHESIS · Ultrahigh-speedclocktreesynthesis minimizes both clock skew and insertion delay · Supportsgatedclocksandmultipleclock domains · Post-routeclocktreeoptimization · Usefulskewanalysisandoptimization ADVANCED POWER PLANNING · Quickpowerplanning, includingstatic and dynamic power consumption analysis · Built-inpower/IRdropanalysis* · Finemeshroutingsupportedwith embedded macro blocks · Power-griddesignresultsinIRdrop numberswithin10%ofSPICE * Interface to signoff power-grid verification requires a Cadence Encounter Power System license, which must be purchased separately. SILICON VIRTUAL PROTOTYPING · BasedonFirstEncountertechnology · Fullgate-levelplacement · Fastdetailedtrialrouting(10xfaster than traditional detailed routers) ­ Increases correlation with the final implementation · Fastanalysiswith2. 5-Dparasitic extraction(10xfasterthantraditional extractors) · Delayandtiminganalysisusing industry-standard timing library and constraints formats · Physicaloptimizationtechnologyfor advanced timing closure · In-placeoptimization(IPO)forcell resizing, buffer insertion, and load splitting ­ Leakage power optimization ­ Advanced logic restructuring option EASE-OF-USE · Easy-to-use, built-insignalandpower wire editing functionality · Tclprogramminginterfacethroughout the flow · Intuitiveandhelpfulcommands · Familiarusemodel · Easy-to-learnsystemletsyourampup within a week · Helpfulreportsforallsteps ROUTING · Industry-provenrouters · Supportsadvancedengineeringchange order (ECO) routing · Wireeditorenvironmentforcustom edits www. cadence. com VIR TUOSO DIGITAL IMPLEMENTATION 2 SPECIFICATIONS INPUT · HDL(tosynthesis):Verilog®, VHDL, SystemVerilog (directives, pragmas) · Logicalandtiminglibrary:libraryformat (. alf), TLF, or. libphysicallibrary:library exchangeformat(LEF) · Mixed-language/mixed-levelnetlist: gate-level netlist in Verilog, gate-level EDIFnetlist · Timingconstraints:Synopsysdesign constraints (SDC) · Floorplaninformation:PDEF · Detailedfloorplaninformation:DEF · Delayinformation:SDF · Interconnectparasitics:DSPF/RSPF, SPEF CADENCE SERVICES AND SUPPORT · Cadenceapplicationengineerscan answer your technical questions by telephone, email, or Internet--they can also provide technical assistance and custom training · Cadencecertifiedinstructorsteach morethan70coursesandbring their real-world experience into the classroom · Morethan25InternetLearningSeries (iLS) online courses allow you the flexibility of training at your own computer via the Internet ·CadenceOnlineSupportgivesyou 24x7onlineaccesstoaknowledgebase of the latest solutions, technical documentation, software downloads, and more OUTPUT · Optimizedgate-levelnetlist(from synthesis) · Netlist:DEF, Verilog · Interconnectparasitics:DSPF, SPICE, SPEF · Delayinformation:SDF · Floorplanandplacement:DEF, PDEF · GDSII PLATFORMS · Linux(32-and64-bit) · Solaris(64-bit) · SOLX86(64-bit) · IBMAIX(64-bit) For more information contact Cadence sales at: +1. 408. 943. 1234 or log on to: www. cadence. com/ contact_us © 2009 Cadence Design Systems, Inc. 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