User manual CADENCE DESIGN SYSTEMS VIRTUOSO MULTI-MODE SIMULATION DATASHEET

[. . . ] These can lead to problems such as performance degradation, burn-in yield loss, leakage current increase leading to increased power consumption, and even functional failure of ICs. Virtuoso UltraSim Full-Chip Simulator XL provides a full-chip reliability simulation and analysis solution, enabling designers to consider reliability effects in the early stages of design and ensure that circuits have sufficient margins to function correctly over their entire lifetimes. SPECIFICATIONS COMPREHENSIVE DEVICE MODELS · MOSFETmodels, includinglatest versions of BSIM3, BSIM4; PSP, HISIM, MOS9, MOS11 and EKV · Silicon-on-insulator(SOI), including latest versions of BTASOI, SSIMSOI BSIMSOI and BSIMSOI PD · High-voltageMOSFETmodels, including latest versions of HVMOS, LDMOS and HiSim_HV · TMImodelsfromTaiwanSemiconductor Manufacturing Company (TSMC) · Bipolarjunctiontransistor(BJT)models, including latest versions of VBIC, HICUM L0, HICUM L2, Mextram, HBT and Gummel-Poon models · GaASMESFETmodels, includinglatest versions of GaAs, TOM2 and TOM3 · RensselaerPolytechnicInstitute's(RPI) Poly and Amorphous Silicon Thin-Film models · Diode, JFET, FinFETandFlashcell models · Verilog-Acompactdevicemodels · Specializedreliabilitymodels(AgeMOS) for Hot Carrier Injection (HTI) and Negative Bias Temperature Instability (NBTI) analysis LANGUAGE AND NETLIST SUPPORT Virtuoso Multi-Mode Simulation is compatible with most commonly used SPICE input decks for both pre- and postlayout. It can natively read Spectre, SPICE, and Verilog-A netlist formats and device models. It also supports standard language inputs in Verilog-AMS, VHDL-AMS, Verilog-A, Verilog®, and VHDL formats. POST-LAYOUT SIMULATION Verification for post-layout designs has become increasingly important with advanced nanometer processes. [. . . ] Users can augment the library by defining their own measurements. ANALOG TURBO FUNCTIONALITY Turbo functionality in Virtuoso Spectre Circuit Simulator XL provides a considerable performance boost over the traditional SPICE-level analog simulation with full SPICE accuracy. The proprietary techniques in the L configuration have been extended to address the challenges designers face with tough complex analog and mixed-signal circuits. Turbo multi-threading allows designers to leverage multi-core machines to achieve additional performance speedup. The use model in turbo mode is identical to SPICE-level simulation offered with the L configuration, enabling designers to preserve their existing setup and methodology. UltraSim Full-Chip Simulator, and Virtuoso AMS Designer with Flexible Analog Simulation. All sweep types are supported in the toolbox including Monte Carlo and parametric. Special data structures are used to store RF signals and harmonics resulting from PSS and QPSS analysis. Furthermore, the Virtuoso Multi-Mode Simulation toolbox complements the rich MATLAB libraries with communication product-specific post-processing functions such as Fast Fourier Transform, thirdorder intercept point, and 1-dB gain compression point. process nodes through better device model manipulation and multi-threading. The "Turbo" use model is identical to RF analysis offered with the XL configuration, enabling designers to preserve their existing setup and methodology. TURBO POST LAYOUT Turbo post-layout enables analog and RF block and subsystem post-layout verification at near the speed of prelayout simulation. An accurate parasitic reduction technique enhances the simulation performance of parasiticdominant circuits by a significant amount over traditional SPICE-level simulation. The technology enables designers to trade-off accuracy and performance using simple user-friendly setup. FEATURES OF VIRTUOSO SPECTRE CIRCUIT SIMULATOR GXL RF ANALYSIS WITH "TURBO" TECHNOLOGY RF analysis with "Turbo" technology provides increased performance enhancement over traditional steady state (Harmonic Balance and shooting Newton) and envelope analysis techniques with full SPICE accuracy. The technology enables complete analysis and verification of large RF circuits designed for advanced CMOS SPECIFICATIONS COMPREHENSIVE CIRCUIT ANALYSIS Virtuoso Spectre Circuit Simulator L · DC, AC, andtransientanalysis · Noise, transferfunction, andsensitivity analysis CO-SIMULATION WITH SIMULINK The MathWorks Simulink interface to Virtuoso Spectre XL offers system and circuit designers a unique integrated environment for design and verification. Designers can insert their analog and RF schematics and post-layout netlist directly in the system-level block diagram and run a co-simulation between Simulink and Virtuoso Spectre technologies. Designers can reuse the same Simulink testbench from system-level design to post-layout verification, thereby minimizing the unnecessary format conversion while maintaining accuracy throughout the design flow. VIRTUOSO MULTI-MODE SIMULATION TOOLBOX FOR MATLAB The Virtuoso Multi-Mode Simulation toolbox for MATLAB reads PSF and SST2 files directly in MATLAB. Users benefit from the rich set of MATLAB mathematical functions to post-process simulation results from Virtuoso Spectre Circuit Simulator L and XL, Virtuoso Figure 4: RF analysis with "Turbo" technology enables fast transceiver verification www. cadence. com VIRTUOSO MULTI-MODE SIMULATION 6 · Transientnoiseanalysis · MonteCarloandparametricstatistical support · Fullsupportforsweepinganalysisand circuit parameters · Built-inmeasurementdescription language Virtuoso Spectre Circuit Simulator GXL · RFSimulationwith"Turbo"Technology · Accurateparasiticreductionforanalog and RF post-layout block verification DESIGN INPUTS/OUTPUTS · VirtuosoSpectrenetlistformat · SPICEnetlistformat · Verilog-A2. 0 · S-Parameterdatafiles · PSFwaveformformat Virtuoso Spectre Circuit Simulator XL · Harmonicbalanceanalysis · Periodicandquasi-periodicsteady state analysis (PSS and QPSS) based on shotting Newton technology · Periodicandquasi-periodicnoise analysis (PNoise, QPNoise) · Periodicandquasi-periodicsmallsignal analysis(PAC, PXF, PSP, QPAC, QPSF, QPSP) · Periodicstabilityanalysis(PSTB) · Time-domainandfrequency-domain envelope analysis · Perturbation-basedrapidIP2andIP3 · Noiseanddistortionsummaries · Co-simulationwithSimulinkfromThe MathWorks · VirtuosoMulti-ModeSimulationtoolbox for MATLAB from the MathWorks · Analogsimulationwith"Turbo" Technology www. cadence. com VIRTUOSO MULTI-MODE SIMULATION 7 V IR TUOSO ACCELER AT E D PA R A L L E L S I M U L AT O R Cadence Virtuoso Accelerated Parallel Simulator, a key component of the Virtuoso Multi-mode Simulator, provides the next generation of analog and RF simulation. It delivers significant scalable performance and capacity at full Spectre accuracy across a broad range of complex analog, RF and mixed-signal blocks and sub-systems with sizes up to millions of transistors, passive and parasitic elements. Virtuoso Accelerated Parallel Simulator provides all the transistor-level analysis capabilities available in Virtuoso Spectre Circuit Simulator. Additionally, Its proprietary parallel simulation technology delivers scalable multi-threading capability on modern multi-processing compute platforms. FEATURES OF VIRTUOSO ACCELERATED PARALLEL SIMULATOR L · Advancedmulti-threadingsimulationon multi-core compute platforms enabling up to 4 cores · Parasiticreductionforpostlayout design enabling even more performance gain for analog and RF designs dominated by parasitics · Verilog-Acompactdevicemodels · Specializedreliabilitymodels(AgeMOS) for Hot Carrier Injection (HTI) and Negative Bias Temperature Instability (NBTI) analysis CIRCUIT ANALYSIS · TransientandDCanalysis · TransientNoiseanalysis · MonteCarloandparametricstatistical support · Fullsupportforsweepinganalysisand circuit parameters · Built-inmeasurementdescription language · RFharmonicbalanceanalysis · RFenvelopeanalysissupportingall modulation schemes · RFnoiseandsmallsignalanalysisbased on harmonic balance solution FEATURES OF VIRTUOSO ACCELERATED PARALLEL SIMULATOR XL · Multi-threadedharmonicbalanceand envelope analysis · FullsupportofRFcomponentsand measurements with identical use model toVirtuosoSpectreCircuitSimulatorXL BENEFITS · Providessignificantsingle-thread performance with full Spectre accuracy · Enableshigh-precisionsimulationfor large post-layout analog designs and subsystems dominated by parasitic devices · Deliversscalableperformance leveraging machines with multiprocessing architectures allowing higher levels of analog design integration and verification. · ProvidesidenticalusemodeltoVirtuoso Spectre Circuit Simulator · Enablesfastandaccurateanalysisof complete transceivers and large postlayout RFIC blocks by significantly improve the performance and capacity of harmonic balance analysis on multiprocessor compute platforms SPECIFICATIONS COMPREHENSIVE DEVICE MODELS · MOSFETmodels, includinglatest versions of BSIM3, BSIM4; PSP, HISIM, high-voltage MOS (HVMOS), MOS9, MOS11 and EKV · Silicon-on-insulator(SOI), including latest versions of BTASOI, SSIMSOI BSIMSOI and BSIMSOI PD · Bipolarjunctiontransistor(BJT)models, including latest versions of VBIC, HICUM, Mextram, HBT and GummelPoon models · Diode, JFETandGaASMESFETmodels · RensselaerPolytechnicInstitute's(RPI) Poly and Amorphous Silicon Thin-Film models DESIGN INPUTS/OUTPUTS · VirtuosoSpectrenetlistformat · SPICEnetlistformat · Verilog-A · S-Parameterdatafiles · PSFwaveformformat www. cadence. com VIRTUOSO MULTI-MODE SIMULATION 8 V IR TUOSO ULTRASIM F U L L - C H I P S I M U L AT O R VIRTUOSO ULTRASIM FULL-CHIP SIMULATOR The Virtuoso UltraSim Full-Chip Simulator is a high-performance transistor-level FastSPICE circuit simulator for pre- and post-layout verification of memories, custom-digital and analog/mixedsignal SoC designs. It delivers the capacity, accuracy and speed required for verification using true hierarchical simulation and patented isomorphic and adaptive partitioning algorithms Digital Test Bench d PM a Mem D a D Analog Hierarchical Netlist Functional Verification AMS Designer and UltraSim Stitching Timing Power Reliability Parasitics DSPF, SPEF BENEFITS · Acceleratespre-andpost-layout simulation for a wide range of applications from blocks to full-chip SoCs (see Figure 5) · Providesacomprehensivesetof transistor-level analysis covering Electrical Rule Check (ERC), power, timingandnodalactivity(seeFigure6) · Handleslargepost-layoutdesignsusing acombinationofuniquehierarchical parasiticstitchingtechniquesandan accuratefrequency-basedparasitic reduction algorithm · Supportsmultiplesimulationmodes (spice, analog, mixed-signal, digital) enabling the user to locally tune performance and accuracy settings for different blocks in the design · Flexibleeasy-to-usecontrolsfor providingadequatetrade-offbetween accuracy and simulation speed · Plugssmoothlyintodesignand verification flows through integration with Virtuoso Analog Design Environment and command-line environments Electromigration/ IR Drop Analysis Figure 5: Virtuoso UltraSim post-layout verification and analysis FEATURES COMPATIBLE WITH SPICE, SPECTRE, VERILOG-A, DSPF, AND SPEF Virtuoso UltraSim Full-Chip Simulator is compatible with most types of SPICE input decks for both pre- and post-layout. Natively reads Virtuoso Spectre format netlists and models, and uses the same views within Virtuoso Analog Design Environment, making it easy to adopt in Virtuoso Spectre-based design flows. POST-LAYOUT SIMULATION When used in conjunction with Cadence post-layout products, Virtuoso UltraSim Full-Chip Simulator provides a means for exploration and validation of such effects as electromigration, IR drop, signal integrity, and substrate degradation. It also has built-in, state-of the-art, S-Parameter­based parasitic reduction for faster simulation with minimal loss in accuracy. Electrical Rule Check MOSFETs connected across different power domains Floating gates, floating bulks, and dangling nodes MOSFET shorting VDD and GND Always conducting MOSFET NMOS-VDD, PMOSGND connections Forward-biased substrate Power Analysis Average, RMS, peak-to-peak power and total energy at the chip and block level Current hot spots Wasted capacitive currents Floating gate-induced leakage Static: DC leakage path Timing Analysis Node-Activity Analysis Glitch check Excessive rise and fall times Overshoot, undershoot, toggling, and note capacitance Signal probablility of being high or low Static: device parameters, voltage checks, and highimpedance nodes Setup, hold, pulse width and timing edge errors User-defined measurements using Spice measure Figure 6: Virtuoso UltraSim transistor-level full-chip analysis www. cadence. com VIRTUOSO MULTI-MODE SIMULATION 9 DESIGN RELIABILITY SIMULATION Virtuoso UltraSim Full-Chip Simulator provides a robust set of analyses capable of predicting and validating timing, power, and reliability. It is the only FastSPICE simulator capable of simulating hot carrier injection (HCI) and negative bias temperature instability (NBTI)--key stress effects that must be taken into account for high-performance advanced node designs. · AMS-VirtuosoUltraSim ­ Verilog-AMS 2. 0 ­ VHDL-AMS1076. 1 ­ Verilog(IEEE1364-1995, IEEE13642001 extensions) ­ VHDL(IEEE1076-1987, IEEE10761993, IEEE1076. 4-2000[VITAL 2000]) ­ PLI 1. 0, VPI (PLI 2. 0) ­ SDF ­ SystemC®, SystemVerilog SPECIFICATIONS DESIGN INPUTS AND OUTPUTS · VirtuosoSpectrenetlist · SPICEnetlistformat · DSPF/SPEFparasiticformats · Verilog-A · SST2waveformformat · PSFandPSFXLwaveformformat · FSDBformat · Veritoolswaveformformat · VirtuosoUltraSim/Verilog ­ Verilog-HDLIEEE1364 ­ PLI 1. 0, VPI (PLI 2. 0) ­ SDF www. cadence. com VIRTUOSO MULTI-MODE SIMULATION 10 V IR TUOSO AMS DES I G N E R S I M U L AT O R Cadence Virtuoso AMS Designer provides an advanced mixed-signal simulation solution for the design and verification of analog, RF, memory, and mixed-signal SoCs. [. . . ] Automatically inserted interface elements are used to translate signals from one domain to the next, leaving the user free to simulate with different design configurations to easily trade off simulation speed for simulation accuracy. · DigitalandRealnumbermodeling capabilities · System-levelsimulationswithlinksto Simulink from the MATHWORKS · Save/restart · Commonmixed-signalwaveform database INCISIVE ENVIRONMENT · Mixed-signaldebugger · Breakpointsontime, position, condition · Debugsteppingthroughbehavioral code, analog, and digital · SourceviewerwithVerilog-AMS/VHDLAMS syntax highlighting · Directvalueaccessinsourceviewer · Waveformwindow · Registerwindow · Calculator · Schematictracer · Signalflowbrowser · Errorbrowser · Digitaltransactionsupport AMS DESIGNER VERIFICATION OPTION AMS Designer Verification Option provides a complete solution for advanced mixed-signal SoC verification. It enables cross-domain connectivity between test benches and design IP blocks from multiple vendors by providing native connectivity between VHDL or SystemVerilog and SPICE. The solution also extends mature digital verification methodologies, such as low power, to the analog domain. SPECIFICATIONS VIRTUOSO ENVIRONMENT · DirectVerilog-AMSnetlisting · HierarchyeditorAMSplug-in AMS DESIGNER VERIFICATION OPTION · NativeVHDL-SPICEconnectivity · NativeSystemVerilogtoSPICEandAMS connectivity · Power-Smartconnectmodulesforlow power support ANALOG-CENTRIC AND DIGITALCENTRIC FLOWS Virtuoso AMS Designer is tightly integrated with the Virtuoso Analog Design Environment for mixed-signal block design. It uses native ADE netlisting technologies to combine schematics and behavioral views enabling users to independently manage the level of abstraction of each block. [. . . ]