User manual DCS (AUDIO) DELIUS

[. . . ] dCS Delius Stereo Digital to Analogue Converter User Manual Software Release 2. 3x September 2004 © dCS Ltd. 1999 - 2004 Price UK £17. 50 / Euro 25. 00 All rights reserved. No part of this publication may be reproduced, stored in or introduced into a retrieval system, or transmitted in any form, or by any means (electronic, mechanical, photocopying, recording or otherwise) without the prior written permission of dCS1. Any person who does any unauthorised act in relation to this publication may be liable to criminal prosecution and civil claims for damages. [. . . ] Press the Purcell button () and the blue LED will light up for about 5 seconds. During this time, the Standby, Function, Input selector, Filter, , and Display buttons will control the Upsampler instead of Delius. Sending a Purcell command will keep the Remote Control in Purcell mode (and the LED on) for another 5 seconds. Press the Purcell button again while the blue LED is lit to return to Delius mode (or just wait 5 seconds). If the blue LED is on, the Upsampler will respond. Phase Button Changes the Phase of the analogue outputs to Inverted. The Phase indicator on the Front Panel will light. Filter Button () () Changes the interpolation filter setting, giving a different trade-off between Nyquist image suppression and energy smear. Each sample rate has a separate Filter setting stored, so Delius must be locked to a suitable source before the Filter setting can be changed. This feature is duplicated in the Menu, see Filter on page 22. Display button () Each press reduces the display brightness on a scale from Bright 7 to Bright 0. Up and Down ( / ) buttons Use these buttons () to change Volume and Balance settings or scroll along the Function Menu, see page 21. Manual filename: Delius Manual v2. 3x. doc English version Page 44 email: more@dcsltd. co. uk web-site: www. dcsltd. co. uk dCS Delius User Manual dCS Ltd Manual for Software Issue 2. 3x September 2004 Manual filename: Delius Manual v2. 3x. doc English version Page 45 email: more@dcsltd. co. uk web-site: www. dcsltd. co. uk dCS Delius User Manual dCS Ltd Manual for Software Issue 2. 3x September 2004 DELIUS TECHNICAL INFORMATION Converter Type · 5-bit, approximately 3MS/s oversampled, dCS patented Ring DAC topology. Digital Interface Specifications AES/EBU (AES3) Type Impedance Sensitivity (unloaded) Maximum Wordlength Connectors Connections Inputs Balanced, differential 110 1 ~ 10 24 XLR3 female (2) Ground or shield +Signal -Signal V pk-pk bits Pin 1 Pin 2 Pin 3 Table 1 ­ AES/EBU Interface Electrical Characteristics SPDIF (electrical) Type Impedance Sensitivity (unloaded) Maximum Wordlength Connectors Input REC Output Single ended, ground referred 75 75 0. 5 1. 0 24 24 RCA Phono RCA Phono & BNC V pk-pk bits Table 2 ­ SPDIF Interface Electrical Characteristics SPDIF (optical) Type Wavelength Maximum Wordlength Connector Toslink Input ST Input Optical 660 850 24 24 Toslink ST EIAJ CP-340 (if fitted) nm bits Table 3 ­ Optical Interface Electrical Characteristics SDIF / Wordclock Type Impedance Sensitivity (unloaded) Connectors Input Output Single ended, ground referred 100 25 TTL TTL BNC BNC Table 4 ­ SDIF / Wordclock Interface Electrical Characteristics Manual filename: Delius Manual v2. 3x. doc English version Page 46 email: more@dcsltd. co. uk web-site: www. dcsltd. co. uk dCS Delius User Manual dCS Ltd Manual for Software Issue 2. 3x September 2004 I/O High speed, multi-channel dCS encrypted DSD 6-way (2) IEEE 1394 Type Data format Connectors Table 5 ­ IEEE 1394 Interface Electrical Characteristics Sample Rates · · · · 32, 44. 1, 48, 88. 2 or 96kS/s on single wire interfaces and SDIF-2 / Wordclock Input, auto selected. Optical inputs are not guaranteed at 88. 2kS/s and 96kS/s. 88. 2, 96, 176. 4 or 192kS/s on Dual AES interface, auto selected. 2. 822MS/s for DSD, requires a 44. 1kHz wordclock. 44. 1kHz for Wordclock Output in master mode, not temperature compensated. Frequency Response (set to Filter 1) · Fs=32kS/s · Fs=44. 1 or 48kS/s · Fs=88. 2 or 96kS/s · Fs=176. 4 or 192kS/s · DSD 6 +/-0. 1dB, 10Hz to 15kHz +/-0. 1dB, 10Hz to 20kHz +/-0. 1dB, 10Hz to 35kHz 5 +0. 25/-0. 35dB, 10Hz to 55kHz +0. 2/-0. 35dB, 10Hz to 55kHz Filter 1 Frequency Responses 0 32k -6 Level (dB) 48k 96k DSD 44. 1k -12 88. 2k 176. 4k 192k -18 -24 0. 02 10 20 30 40 50 Tone Frequency (kHz) 60 70 80 90 100 Figure 10 ­ Frequency responses at all sample rates, set to Filter 1 5 The point of high sample rates is not to have a ruler flat response with a brick-wall filter. See for example "Effects in High Sample Rate Audio Material" by M. J. Story, R. Kelly, D. A. Macleod th & M. N. Harris, presented at the 20 Tonmeister Tagung at Karlsruhe in 1998. Manual filename: Delius Manual v2. 3x. doc English version Page 47 email: more@dcsltd. co. uk web-site: www. dcsltd. co. uk dCS Delius User Manual dCS Ltd Volume Control · Balance Control · · De-Emphasis · Analogue Outputs Balanced Balanced, not floating < 1 + 100µH 600 < -110 < -100 < -90 6 or 2 XLR male (2) +Signal on pin 2 -Signal on pin 3 Manual for Software Issue 2. 3x September 2004 Digitally implemented, 0 to ­60dB in 0. 5dB steps Digitally implemented, 0 to ­40dB in variable steps, each side. Mutes one channel at minimum settings. Auto-selected, 50/15µs, CCITT J17 or none, available at 32, 44. 1 or 48kS/s. Type Source impedance (20Hz-20kHz) Maximum load Noise, unweighted (20Hz-20kHz) Spurious responses (20Hz-20kHz) L-R crosstalk, (20Hz-20kHz) Level for full scale (set by the Out menu) Connectors Connections Unbalanced Single ended, ground referred < 1 + 100µH 600 < -105 < -100 < -90 6 or 2 RCA Phono (2) dB0 dB0 dB V rms Table 6 ­ Analogue Output Electrical Characteristics Clocking The sample clock quality significantly determines the output performance of the converter. The highest quality clocks that are available are crystals, so we use these. Delius uses two on-board voltage controlled crystal oscillators (VCXO's) as clock sources - one for the 44. 1kS/s related outputs and one for the 48kS/s related outputs. In slave mode, the active VCXO is synchronised to the clock signal extracted from the input by a phase locked loop (PLL). This PLL is of a special narrow bandwidth type, that provides a significant degree of "clock cleaning". The PLL is also very robust, and will lock to very poor signals if necessary. Data is decoded using a much wider band (faster) PLL, so AES3 type low frequency jitter on the input clock can be handled, and will be cleaned. [. . . ] 69 U unbalanced outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Up and Down buttons, remote . . . . . . . . . . . . . . . . . . . . . . 44 updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 42, 62 updates, hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ]