User manual FERGUSON TE-A20 SERVICE MANUAL

[. . . ] The TE-A20 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E ) controls, which eliminate bus contention issues. This device is designed to allow either single (or multiple) Sector or full chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector. This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications. ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 TE-A20 TABLE 1. [. . . ] The procedure requires a high voltage (VID) on address pin A9 and the control pins. for an additional supplement on this feature. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 TE-A20 WRITE OPERATION STATUS DQ7 DATA Polling The TE-A20 provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6) When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse. DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles. ) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7­DQ0 at least twice in a row to determine whether a toggle bit is toggling. [. . . ] B, Issue Date: 2004/04/01 TE-A20 Table 15. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 125°C 20 Years Test Conditions 150°C Min 10 Unit Years This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 TE-A20 SWITCHING WAVEFORMS Figure 5. AC Waveforms for READ Operations Figure 6. [. . . ]