User manual FREESCALE MC13213

[. . . ] MC13211/212/213 ZigBeeTM- Compliant Platform 2. 4 GHz Low Power Transceiver for the ® 802. 15. 4 Standard plus Microcontroller IEEE Reference Manual Document Number: MC1321xRM Rev. 1. 3 04/2008 How to Reach Us: Home Page: www. freescale. com E-mail: support@freescale. com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale. com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale. com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support. japan@freescale. com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. [. . . ] MC1321X Memory Maps MC1321x Reference Manual, Rev. 1. 3 Freescale Semiconductor 11-1 MCU Memory Note that the MC13213 has a high ~60k block of flash memory and a second smaller ~2k low block of flash memory. The high block can be fully protected while the low block is left writable for storing parameters and data as non volatile values. 11. 1. 1 Reset and Interrupt Vector Assignments Table 11-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the HCS08. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 12, "MCU Resets, Interrupts, and System Configuration". Table 11-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0:FFC1 Unused Vector Space (available for user program) 0xFFCA:FFCB 0xFFCC:FFCD 0xFFCE:FFCF 0xFFD0:FFD1 0xFFD2:FFD3 0xFFD4:FFD5 0xFFD6:FFD7 0xFFD8:FFD9 0xFFDA:FFDB 0xFFDC:FFDD 0xFFDE:FFDF 0xFFE0:FFE1 0xFFE2:FFE3 0xFFE4:FFE5 0xFFE6:FFE7 0xFFE8:FFE9 0xFFEA:FFEB 0xFFEC:FFED 0xFFEE:FFEF 0xFFF0:FFF1 0xFFF2:FFF3 0xFFF4:FFF5 0xFFF6:FFF7 0xFFF8:FFF9 0xFFFA:FFFB RTI IIC ATD Conversion Keyboard SCI2 Transmit SCI2 Receive SCI2 Error SCI1 Transmit SCI1 Receive SCI1 Error SPI TPM2 Overflow TPM2 Channel 4 TPM2 Channel 3 TPM2 Channel 2 TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow TPM1 Channel 2 TPM1 Channel 1 TPM1 Channel 0 ICG Low Voltage Detect IRQ Vrti Viic1 Vatd1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch4 Vtpm2ch3 Vtpm2ch2 Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vector Vector Name MC1321x Reference Manual, Rev. 1. 3 11-2 Freescale Semiconductor MCU Memory Table 11-1. Reset and Interrupt Vectors (continued) Address (High/Low) 0xFFFC:FFFD 0xFFFE:FFFF Vector SWI Reset Vector Name Vswi Vreset 11. 2 Register Addresses and Bit Assignments The registers in the HCS08 are divided into these three groups: · Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. · High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. · The non volatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0­0xFFBF. Non volatile register locations include: -- Three values which are loaded into working registers at reset -- An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the non volatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 11-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 11-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 11-3 and Table 11-4 the whole address in column one is shown in bold. In Table 11-2, Table 11-3, and Table 11-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC1321x Reference Manual, Rev. [. . . ] 0 R/W is not used in comparison A 1 R/W is used in comparison A R/W Comparison Value for Comparator B -- When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle Enable R/W for Comparator B -- Controls whether the level of R/W is considered for a comparator B match. 0 R/W is not used in comparison B 1 R/W is used in comparison B 5 TAG 4 BRKEN 3 RWA 2 RWAEN 1 RWB 0 RWBEN MC1321x Reference Manual, Rev. [. . . ]