User manual FUJITSU MPB3032AT

[. . . ] MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVES PRODUCT MANUAL C141-E045-02EN REVISION RECORD Edition 01 02 Date published August. , 1997 March, 1998 All pages revised. Revised contents Specification No. : C141-E045-**EN The contents of this manual is subject to change without prior notice. Copyright © 1998 FUJITSU LIMITED C141-E045-02EN i PREFACE This manual describes the MPB3021AT/MPB3032AT/MPB3043AT/MPB3052AT/MPB3064AT, a 3. 5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. [. . . ] / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (6) WRITE MULTIPLE (X'C5') This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command. The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the Status register is required to set only at the start of the data block, not on each sector. The number of sectors (block count) to be transferred without interruption is specified by the SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command. When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block). Upon receipt of this command, the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0). If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of ("number of sectors"/"block count"). If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error. Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred. Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block. C141-E045-02EN 5 - 23 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 × 1 L 0 × 0 DV 0 1 0 1 Start head No. / LBA [LSB] Transfer sector count xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Note: When the command terminates due to error, only the DV bit and the error information field are valid. × L × Status information DV End head No. / LBA [LSB] 00H Error information (7) WRITE DMA (X'CA' or X'CB') This command operates similarly to the WRITE SECTOR(S) command except for following events. · · · The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. [. . . ] However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function. C141-E045-02EN 6 - 23 Comments concerning this manual can be directed to one of the following addresses: FUJITSU LIMITED Business Planning Solid Square East Tower 580 Horikawa-cho, Saiwai-ku, Kawasaki, 210-0913, Japan TEL: 81-44-540-4056 FAX: 81-44-540-4123 FUJITSU COMPUTER PRODUCTS OF AMERICA, INC. [. . . ]