User manual FUJITSU MPE3XXXAT

[. . . ] MPE3xxxAT DISK DRIVES PRODUCT MANUAL C141-E077-01EN REVISION RECORD Edition 01 Date published June, 1999 Revised contents Specification No. : C141-E077-**EN The contents of this manual is subject to change without prior notice. Copyright © 1999 FUJITSU LIMITED C141-E077-01EN i This page is intentionally left blank. PREFACE This manual describes the MPE3xxxAT series, a 3. 5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems. [. . . ] At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 × 1 L 0 × 0 DV 0 1 0 1 Start head No. / LBA [LSB] Transfer sector count xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Note: When the command terminates due to error, only the DV bit and the error information field are valid. × L × Status information DV End head No. / LBA [LSB] 00H Error information (7) WRITE DMA (X'CA' or X'CB') This command operates similarly to the WRITE SECTOR(S) command except for following events. · · · The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer. When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command. A host system can be select the following transfer mode using the SET FEATURES command. 5 - 24 C141-E077-01EN 1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) R = 0 or 1 At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × L × Status information DV End head No. /LBA [MSB] 1 × 1 L 0 × 0 DV 1 0 1 R Start head No. / LBA [LSB] Transfer sector count xx End cylinder No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (8) WRITE VERIFY (X'3C') This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 × 0 L 1 × 1 DV 1 1 0 0 Start head No. / LBA [LSB] Transfer sector count xx C141-E077-01EN 5 - 25 At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × L × Status information DV End head No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (9) RECALIBRATE (X'1x', x: X'0' to X'F') This command performs the rezero. Upon receipt of this command, the device sets BSY bit of the Status register and performs a rezero. When the device completes the rezero, the device updates the Status register, clears the BSY bit, and generates an interrupt. This command can be issued in the LBA mode. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 × 0 × 0 × 1 DV xx xx xx xx xx x x xx x x At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx 5 - 26 C141-E077-01EN (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1. [. . . ] However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function. C141-E077-01EN 6 - 21 Comments concerning this manual can be directed to one of the following addresses: FUJITSU LIMITED Business Planning Solid Square East Tower 580 Horikawa-cho, Saiwai-ku, Kawasaki, 210-0913, Japan TEL: 81-44-540-4056 FAX: 81-44-540-4123 FUJITSU COMPUTER PRODUCTS OF AMERICA, INC. [. . . ]