User manual KINGSTON KVR667D2S4F52G MEMORY MODULE SPECIFICATIONS

[. . . ] Memory Module Specifications KVR667D2S4F5/2G 2GB 256M x 72-Bit PC2-5300 CL5 ECC 240-Pin FBDIMM Description: This document describes ValueRAM's 2GB (256M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully buffered" ECC "single rank" memory module. This module is based on eighteen 256M x 4-bit 667MHz DDR2 FBGA components. [. . . ] System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency 2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility VALUERAM0547-001. A00 Page 3 TECHNOLOGY Functional Block Diagram: VSS S0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DM CS DQS DQS DM DQS9 DQS9 CS DQS DQS DM CS DQS DQS Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA I/O 0 I/O 1 I/O 2 I/O 3 D0 DQ4 DQ5 DQ6 DQ7 DQS10 DQS10 I/O 0 I/O 1 I/O 2 I/O 3 D9 DM VTT CS DQS DQS Terminators AMB SPD, AMB D0-D17, AMB D0-D17 D0-D17, SPD, AMB VTT DQ8 DQ9 DQ10 DQ11 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 DQS8 CB0 CB1 CB2 CB3 PN0-PN13 PN0-PN13 PS0-PS9 PS0-PS9 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0-DQS17 SCL SDA SA1-SA2 SA0 RESET SCK/SCK I/O 0 I/O 1 I/O 2 I/O 3 DM D1 DQ12 DQ13 DQ14 DQ15 DQS11 DQS11 I/O 0 I/O 1 I/O 2 I/O 3 DM VCC VDDSPD VDD D10 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D2 DQ20 DQ21 DQ22 DQ23 DQS12 DQS12 VREF VSS All address/command/control/clock I/O 0 I/O 1 I/O 2 I/O 3 DM D11 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D3 DQ28 DQ29 DQ30 DQ31 DQS13 DQS13 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D12 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D4 DQ36 DQ37 DQ38 DQ39 DQS14 DQS14 DQ44 DQ45 DQ46 DQ47 DQS15 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQS16 I/O 0 I/O 1 I/O 2 I/O 3 DM D13 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D5 I/O 0 I/O 1 I/O 2 I/O 3 DM D14 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D6 I/O 0 I/O 1 I/O 2 I/O 3 DM D15 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D7 DQ60 DQ61 DQ62 DQ63 DQS17 DQS17 CB4 CB5 CB6 CB7 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D16 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D8 SN0-SN13 SN0-SN13 SS0-SS9 SS0-SS9 I/O 0 I/O 1 I/O 2 I/O 3 D17 A M B S0 -> CS (all SDRAMs) CKE0 -> CKE (all SDRAMs) ODT -> ODT (all SDRAMs) BA0-BA2 (all SDRAMs) A0-A15 (all SDRAMs) RAS (all SDRAMs) CAS (all SDRAMs) WE (all SDRAMs) CK/CK (all SDRAMs) Notes: 1. DQ-to-I/O wiring may be changed within a nibble. There are two physical copies of each address/command/control/clock VALUERAM0547-001. A00 Page 4 TECHNOLOGY Architecture: Advanced Memory Buffer Pin Description: Pin Name Pin Description Count FB-DIMM Channel Signals SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] FBDRES System Clock Input, positive line System Clock Input, negative line Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines To an external precision calibration resistor connected to Vcc 99 1 1 14 14 10 10 14 14 10 10 1 DDR2 Interface Signals DQS[8:0] DQS[8:0] DQS[17:9]/DM[8:0] DQS[17:9] DQ[63:0] CB[7:0] A[15:0]A, A[15:0]B BA[2:0]A, BA[2:0]B RASA, RASB CASA, CASB WEA, WEB ODTA, ODTB CS[1:0]A, CS[1:0]B CLK[3:0] CLK[3:0] DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Data Strobes, positive lines Data Strobes, negative lines Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. Data Strobes (x4 DRAM only), negative lines Data Checkbits Addresses. A10 is part of the pre-charge command Bank Addresses Part of command, with CAS, WE, and CS[1:0]. Part of command, with RAS, WE, and CS[1:0]. Part of command, with RAS, CAS, and CS[1:0]. On-die Termination Enable Chip Select (one per rank) 175 9 9 9 9 64 8 32 6 2 2 2 2 4 4 CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank) CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. [. . . ] Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands. Reserved for Future Use 2 163 1 1 1 6 5 1 1 129 18 Tie to ground to set functionality as buffer on DIMM. Power/Ground Signals VCC VCCFBD VDD VDDSPD VSS AMB Core Power (1. 5 Volt) AMB Channel I/O Power (1. 5 Volt) AMB DRAM I/O Power (1. 8 Volt) SPD Power (3. 3 Volt) Ground 213 24 8 24 1 156 Total System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency. 655 VALUERAM0547-001. A00 Page 6 TECHNOLOGY Package Dimensions: Advanced Memory Buffer AMB (Units = millimeters) 0. 346 (8. 8) MAX with heat sink Units: inches (millimeters) 45°x 0. 0071(0. 18) 0. 047 (1. 19) 0. 042 (1. 06) 0. 042 (1. 06) 0. 054 (1. 37) 0. 046 (1. 17) Detail A VALUERAM0547-001. A00 Page 7 [. . . ]