User manual MATLAB EDA SIMULATOR LINK 3

[. . . ] EDA Simulator LinkTM 3 User's Guide How to Contact The MathWorks Web Newsgroup www. mathworks. com/contact_TS. html Technical Support www. mathworks. com comp. soft-sys. matlab suggest@mathworks. com bugs@mathworks. com doc@mathworks. com service@mathworks. com info@mathworks. com Product enhancement suggestions Bug reports Documentation error reports Order status, license renewals, passcodes Sales, pricing, and general information 508-647-7000 (Phone) 508-647-7001 (Fax) The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098 For contact information about worldwide offices, see the MathWorks Web site. EDA Simulator LinkTM User's Guide © COPYRIGHT 2003­2010 by The MathWorks, Inc. The software described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement. [. . . ] "Overview to Coding HDL Modules for Simulink Component Simulation" on page 4-8 "Specifying Port Direction Modes in the HDL Module for Component Simulation" on page 4-8 "Specifying Port Data Types in the HDL Module for Component Simulation" on page 4-9 "Compiling and Elaborating the HDL Design for Component Simulation" on page 4-10 Overview to Coding HDL Modules for Simulink Component Simulation The EDA Simulator Link interface passes all data between the HDL simulator and Simulink as port data. The EDA Simulator Link software works with any existing HDL module. However, when you code an HDL module that is targeted for Simulink verification, you should consider the types of data to be shared between the two environments and the direction modes. Specifying Port Direction Modes in the HDL Module for Component Simulation In your module statement, you must specify each port with a direction mode (input, output, or bidirectional). The following table defines these three modes. 4-8 Code an HDL Component for Use with Simulink Applications Use VHDL Mode. . . IN OUT INOUT Use Verilog Mode. . . input output inout For Ports That. . . Represent signals that can be driven by a MATLAB function Represent signal values that are passed to a MATLAB function Represent bidirectional signals that can be driven by or pass values to a MATLAB function Specifying Port Data Types in the HDL Module for Component Simulation This section describes how to specify data types compatible with MATLAB for ports in your HDL modules. For details on how the EDA Simulator Link interface converts data types for the MATLAB environment, see "Performing Data Type Conversions" on page 7-5. Note If you use unsupported types, the EDA Simulator Link software issues a warning and ignores the port at run time. For example, if you define your interface with five ports, one of which is a VHDL access port, at run time, then the interface displays a warning and your code sees only four ports. Port Data Types for VHDL Entities In your entity statement, you must define each port that you plan to test with MATLAB with a VHDL data type that is supported by the EDA Simulator Link software. The interface can convert scalar and array data of the following VHDL types to comparable MATLAB types: · STD_LOGIC, STD_ULOGIC, BIT, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR, and BIT_VECTOR · INTEGER and NATURAL · REAL 4-9 4 Replacing an HDL Component with a Simulink Algorithm · TIME · Enumerated types, including user-defined enumerated types and CHARACTER The interface also supports all subtypes and arrays of the preceding types. Note The EDA Simulator Link software does not support VHDL extended identifiers for the following components: · Port and signal names used in cosimulation · Enum literals when used as array indices of port and signal names used in cosimulation However, the software does support basic identifiers for VHDL. In your module definition, you must define each port that you plan to test with MATLAB with a Verilog port data type that is supported by the EDA Simulator Link software. The interface can convert data of the following Verilog port types to comparable MATLAB types: · reg · integer · wire Note EDA Simulator Link software does not support Verilog escaped identifiers for port and signal names used in cosimulation. However, it does support simple identifiers for Verilog. Compiling and Elaborating the HDL Design for Component Simulation Refer to the HDL simulator documentation for instruction in compiling and elaborating the HDL design. 4-10 Create Simulink Model for Component Cosimulation with the HDL Simulator Create Simulink Model for Component Cosimulation with the HDL Simulator In this section. . . "Creating the Simulink Model for Component Cosimulation" on page 4-11 "Running and Testing a Component Hardware Model in Simulink" on page 4-11 "Adding a Value Change Dump (VCD) File to Component Model (Optional)" on page 4-11 Creating the Simulink Model for Component Cosimulation For the most part, there is nothing different about creating a Simulink model to act as an HDL component than there is from creating a Simulink model to use as a test bench. When using Simulink as a component, you may have multiple HDL Cosimulation blocks rather than a single HDL Cosimulation block, though there's no limitation on how many HDL Cosimulation blocks you may use in either situation. Create a Simulink test bench model by adding Simulink blocks from the Simulink Block libraries. For help with creating a Simulink model, see the Simulink documentation. Running and Testing a Component Hardware Model in Simulink If you design a Simulink model first, run and test your model thoroughly before replacing or adding hardware model components as EDA Simulator Link Cosimulation blocks. Adding a Value Change Dump (VCD) File to Component Model (Optional) You might want to add a VCD file to log changes to variable values during a simulation session. See Chapter 5, "Recording Simulink Signal State 4-11 4 Replacing an HDL Component with a Simulink Algorithm Transitions for Post-Processing" for instructions on adding the To VCD File block. 4-12 Launch HDL Simulator for Component Cosimulation with Simulink Launch HDL Simulator for Component Cosimulation with Simulink In this section. . . "Starting the HDL Simulator from MATLAB" on page 4-13 "Loading an Instance of an HDL Module for Component Cosimulation" on page 4-13 Starting the HDL Simulator from MATLAB The options available for starting the HDL simulator for use with Simulink vary depending on whether you run the HDL simulator and Simulink on the same computer system. If both tools are running on the same system, start the HDL simulator directly from MATLAB by calling the MATLAB function vsim, nclaunch, or launchDiscovery. Alternatively, you can start the HDL simulator manually and load the EDA Simulator Link libraries yourself. Either way, see "Using EDA Simulator Link with HDL Simulators ". Loading an Instance of an HDL Module for Component Cosimulation Incisive users load an instance of the HDL module for cosimulation using the hdlsimulink function. [. . . ] 6 Select Always Generate HDL if you want updated HDL with the project. Note If you do not select this option, you can use the Simulink HDL Coder pane to generate code for the model. Note EDA Simulator Link software makes the target device unavailable because that device's value depends on what board you select. The link software selects that for you automatically. Continue on to "Generate FPGA Project" on page 15-7. Generate FPGA Project Press Generate FPGA HIL button. This process can take some time, as it involves synthesis and bitstream creation for the FPGA and the DSP. [. . . ]