User manual MAXTOR D540X-4K 11-1-2001

[. . . ] TG D OG XQ0 NCWPC/ VEWFQT2 6# $) - :& TQVZC/ © November 1, 2001 Maxtor Corporation. Printed in U. S. A. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein ­ which will be incorporated in revised editions of the publication. Maxtor may make changes or improvements in the product(s) described in this publication at any time and without notice. UL/CSA/VDE/TUV UL standard 1954 recognition granted under File No. [. . . ] This information is processed in the controller ASIC/microprocessor, and a control signal is output to the VCM in the Power ASIC. This controls the current in the actuator coil which controls the position of the actuator. The Read/Write interface allows the integrated µprocessor, disk controller to communicate with the Read/Write chip. The ATA Interface Controller portion of the ASIC provides data handling, bus control, and transfer management services for the ATA interface. Configuration and control of the interface is accomplished by the µController across the MAD bus. Data transfer operations are controlled by the Buffer Controller module. The Motor Controller controls the spindle and voice coil motor (VCM) mechanism on the drive. The Read/Write ASIC integrates an Advanced Partial Response Maximum Likelihood (PRML) processor, a selectable code rate Encoder-Decoder (ENDEC), and a Servo Processor with data rates up to 270 MHz (259 Mb/s). Programming is done through a fast 40 MHz serial interface. The controller and data interface through an 8-bit wide data interface. The Read/Write ASIC is a low power 3. 3 Volts, single supply, with selective power down capabilities. The Read/Write ASIC comprises 12 main functional modules (described below): · Pre-Compensator · Variable Gain Amplifier (VGA) · Butterworth Filter Maxtor D540X-4K 20. 4/40. 0/60. 0/80. 0 GB AT 5-7 Basic Principles of Operation · Flash A/D Converter · Viterbi Detector · ENDEC · Servo Processor · Clock Synthesizer · PLL · Serial Interface · TA Detection and Correction 5-8 Maxtor D540X-4K 20. 4/40. 0/60. 0/80. 0 GB AT TGVNK( GUPQRUG4 GUNWRO+ GVKPK( 4+( #)8 TGKHKNRO# PKC) GNDCKTC8 TGVTGXPQ% &# JUCN( TG\KUGJVP[5 MEQN% TGVNK( JVTQYTGVVW$ TQVCUPGROQ% GT2 TQUUGEQT2 QXTG5 TQVEGVG& KDTGVK8 %'&0' . . 2 The pre-compensator introduces pre-compensation to the write data received from the sequencer module in the DCIIA. The pre-compensated data is then passed to the R/W Pre-Amplifier and written to the disk. Pre-compensation reduces the write interference from adjacent write bit. Digital and analog controlled AGC function with input attenuator for extended range. Continuous time data filter which can be programmed for each zone rate. Digitally controlled and programmable filter for partial response signal conditioning. Provides very high speed digitization of the processed read signal. Decodes ADC result into binary bit stream. Provides 16/17 or 24/25 code conversion to NRZ. Includes preamble and sync mark generation and detection. Servo processor with servo data recovery and burst demodulation. Provides programmable frequencies for each zone data rate. Provides digital read clock recovery. Basic Principles of Operation TGXKT& GVKT9 FPC TGKHKNRO#GT2 PQKVEGTTQ% FPC PQKVEGVG& #6 5'476#'( '4#9/4+( IPKJEC% GXKVRCF# GECHTGVP+ NCKTG5 IPKJEC% MUK& GJEC% FCG4 High speed interface for digital control of all internal blocks. Detects thermal asperities' defective sectors and enables thermal asperity recoveries. The PreAmplifier and Write Driver provides write driver and read pre-amplifier functions, and R/W head selection. The write driver receives precompensated write data from the PreCompensator module in the Read/Write ASIC. The write driver then sends this data to the heads in the form of a corresponding alternating current. The read pre-amplifier amplifies the low-amplitude voltages generated by the R/W heads, and transmits them to the VGA module in the Read/Write ASIC. Head select is determined by the controller. The preamp also contains internal compensation for thermal asperity induced amplitude variation. This section describes the following firmware features: · Disk caching · Head and cylinder skewing · Error detection and correction · Defect management The Maxtor D540X-4K AT hard disk drives incorporate DisCache, a 380 K (minimum) disk cache, to enhance drive performance. This integrated feature is userprogrammable and can significantly improve system throughput. Read and write caching can be enabled or disabled by using the Set Configuration command. The cache buffer for the Maxtor D540X-4K drives features adaptive segmentation for more efficient use of the buffer's RAM. With this feature, the buffer space used for read and write operations is dynamically allocated. The cache can be flexibly divided into several segments under program control. A cache entry consists of the requested read data plus its corresponding prefetch data. Adaptive segmentation allows the drive to make optimum use of the buffer. [. . . ] Hard disks are generally made of aluminum or magnesium alloy (or glass, for optical disks) while the substrate of floppies is usually mylar. SURFACE ­ The top or bottom side of the platter which is coated with the magnetic material for recording data. On some drives one surface may be reserved for positioning information. U UNFORMATTED CAPACITY ­ The total number of bytes of data that could be fit onto a disk. Formatting the disk requires some of this space to record location, boundary definitions, and timing information. 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