User manual MAXTOR ST31081A

[. . . ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST31081A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST31621A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATA Interface Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST31081A/ST31621A Intelligent Disk Drive Product Manual Production Release per ECO SJD7262 P/N 20401030-001 Revision A May 1996 920 Disc Drive Scotts Valley, California 95066 FCC Notice This equipment generates and uses radio frequency energy and, if not installed and used properly; that is, in strict accordance with the manufacturer's instructions, may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class B computing device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference in a residential installation. [. . . ] When the command is issued, the drive sets BSY, stores the required parameter information in the sector buffer, sets the DRQ bit, and generates an interrupt. The host may then read the information out of the sector buffer. The parameter words in the buffer are arranged as follows. All reserved bits or words should be zeroes. All numbers are given in hexadecimal format, rightjustified. Word (hex): 0 1 2 3 4 5 6 7 8 9 10-19 20 21 22 23-26 27-46 47 Description: General configuration bit significant information (0C5A) Default number of logical cylinders Reserved Default number of logical heads Vendor specific (Obsolete) Vendor specific (Obsolete) Default Number of logical sectors per logical track Vendor specific (Obsolete) Vendor specific (Obsolete) Vendor specific (Obsolete) Serial number right justification Vendor specific (Obsolete) Vendor specific (Obsolete) Number of ECC bytes on R/W long commands Controller firmware revision Model number Number of sectors per interrupt on Multiple commands: · bits 15-8: 80H · bits 7-0: 00H means Read/Write multiple not implemented; xxH is the maximum number of sectors that can be transferred per multiple command Reserved 48 Page 52 ST31081A/ST31621A Command Set Chapter 7 Word (hex): 49 Description: Capabilities definitions bits 15-14 0 = (reserved) bit 13 1 = Standby timer as specified in ATA bit 12 0 = (reserved) bit 11 1 = IORDY supported bit 10 1 = IORDY can be disabled bit 9 1 = LBA supported bits 8 1 = DMA supported bits 7-1 0 = (vendor specific) bits 0 1 = assign alternate supported (vendor specific) Reserved bits 15-8 bits 7-0 PIO data transfer cycle timing mode (w/o IORDY) Vendor specific = DMA data transfer timing mode Vendor specific Reserved 1 = the fields reported in words 64-70 are valid 0 = the fields reported in words 64-70 are not valid bit 0 1 = the fields reported in words 54-58 are valid 0 = the fields reported in words 54-58 are not valid 50 51 52 bits 15-8 bits 7-0 53 bits 15-2 bit 1 54 55 56 57 58 59 Number of current logical cylinders Number of current logical heads Number of current sectors per logical track LSW Current capacity in sectors MSW Current capacity in sectors bits bit bits 15-9 8 7-0 Reserved 1 = Multiple sector setting is valid xx = current setting for number of sectors per transfer on R/W Multiple commands 60 61 62 LSW Total number of user addressable sectors (LBA mode only) MSW Total number of user addressable sectors (LBA mode only) bits 15-8 bits 7-0 Vendor specific (Obsolete) Vendor specific (Obsolete) Technical Reference Manual Page 53 Chapter 7 Command Set Word (hex): 63 Description: bits 15-8 bits 7-3 bit 2 bit bit 1 0 01H = Multiword DMA transfer mode active reserved for future Multiword DMA transfer modes** 1 = Multiword DMA transfer Mode 2 supported 0 = Multiword DMA transfer Mode 2 NOT supported 1 = Multiword DMA transfer Mode 1 supported 0 = Multiword DMA transfer Mode 1 NOT supported 1 = Multiword DMA transfer Mode 0 supported 0 = Multiword DMA transfer Mode 0 NOT supported Reserved reserved for future Advanced PIO Modes*** 1 = PIO Mode 4 supported 0 = PIO Mode 4 not supported 1 = PIO Mode 3 supported 0 = PIO Mode 3 not supported 64 bits 15-8 bits 7-2 bit 1 bit 0 65 66 67 68 69-128 129-133 134 Minimum multiword DMA transfer cycle time per word (ns) Recommended multiword DMA transfer cycle time (ns) Minimum PIO transfer cycle time without flow control (ns) Minimum PIO transfer cycle time with IORDY flow control (ns) Reserved Vendor specific (not used) bit 15-2: reserved bit 1: ATA/CAM compliant bit 0: 1= current logical numbers, 0 = default logical numbers Vendor specific Reserved 135-159 160-255 * PIO Timing Parameters Cycle Time ** Multiword DMA Timing Cycle Time *** Advanced PIO Timing Cycle Time Mode 0 (nsec) 600 Mode 0 (nsec) 480 Mode 1 (nsec) 383 Mode 1 (nsec) >= 150 Mode 2 (nsec) 240 Mode 2 (nsec) >= 120 Mode 3 (nsec) >= 180 Mode 4 (nsec) >= 120 Page 54 ST31081A/ST31621A Command Set Chapter 7 Initialize Device Parameters Command Number: 91 hex Description: This command enables the host to set the head switch and cylinder increment points for multiple sector operations. The drive calculates the number of available logical cylinders based upon the total number of available blocks and the values contained in the Sector Count and Drive/Head registers. The sector and head values in the Task File are not checked for validity by this command. If they are invalid, no error will be reported until an illegal access is made by some other command. Cylinder head increments on subsequent commands will occur after access of the maximum sector and maximum head specified by this command. Upon receipt of the command, the drive sets BSY, saves the parameters, resets BSY, and generates an interrupt. Seagate has established a Universal Translate Mode which enables the you to configure the drive in an AT environment to any cylinder, head, and sector configuration desired (refer to chapter 3). Technical Reference Manual Page 55 Chapter 7 Command Set Power Commands Command Number: Ex hex Description: The Power commands are supported on some Seagate drives, including the ST32161A. If a Power command is issued to a drive that does not support the Power commands, an Abort status will be returned to the host in the Error register. Commands E0 through E3 and E5-E6 constitute the Power commands. The following table describes these commands: Error Code: E0H E1H E2H Description: The drive enters Standby Mode immediately The drive enters Idle Mode immediately The drive enters Standby Mode immediately. If the Sector Count register is non-zero, then the Auto Power-Down feature is enabled and will take effect when the drive returns to Idle Mode. If the Sector Count register is zero, then the Auto Power-Down feature is disabled. E3H The drive enters Idle Mode immediately. If the Sector Count register is non-zero, then the Auto Power-Down feature is enabled and will take effect immediately. If the Sector Count register is zero, then the Auto Power-Down feature is disabled. E5H Puts FF hex in the Sector Count register if the drive is in Idle Mode. Puts 00 hex in the Sector Count register if the drive is in, going to, or recovering from the Standby Mode. Puts BB hex in the Sector Count register if power lock is enabled. E6H The drive enters Sleep Mode. A reset is required to bring the drive out of Sleep Mode. Note: Minimum power off/on cycle time is 60 seconds. Page 56 ST31081A/ST31621A Command Set Chapter 7 All of the Power commands except command E6 will execute immediately and return the ending interrupt after the spin up/down sequence is initiated. Please note that if the drive is already spinning (Idle Mode) and a spin-up command is issued from the host, the spin-up sequence is not initiated. [. . . ] Device selection - A device is selected when the DEV bit of the Drive/Head register is equal to the device number assigned to the device by means of a Device 0/Device 1 jumper or switch, or use of the CSEL signal. DMA (Direct memory access) - A means of data transfer between device and host memory without host processor intervention. Head, physical - A transducer which translates the fluctuations in the magnetic orientation of the recording layer of the disk into electrical signals that can be decoded into bits of data. Head, logical - A mapping of sectors on the disk drive into an imaginary surface of a disk for purposes of achieving compatibility with legacy addressing schemes. Technical Reference Manual Page 83 Chapter 8 Error Reporting LBA (Logical block address) - This term defines the addressing of the device as being by the linear mapping of sectors. [. . . ]