User manual MSI P7N SLI V1.0

[. . . ] P7N SLI Series MS-7380 (v1. X) Mainboard G52-73801X5 i Copyright Notice T he material in this doc ument is the intellec tual property of M ICRO-STAR INTERNATIONAL. We take every care in the preparation of this document, but no guarantee is given as to the correctness of its contents. Our products are under continual improvement and we reserve the right to make changes without notice. Trademarks All trademarks are the properties of their respective owners. NVIDIA, the NVIDIA logo, DualNet, and nForce are registered trademarks or trademarks of NVIDIA Corporation in the United States and/or other countries. [. . . ] This item allows you to select the CPU Front Side Bus clock frequency (in MHz). Memory Clock (M Hz) W hen the System Clock Mode sets to [Manual], the field is adjustable. This item allows you to select the memory clock frequency (in MHz). Advance DRAM Configuration Press <Enter> to enter the sub-menu and the following screen appears. M emory Timings This field has the capacity to automatically detect all of the DRAM timing. If you set this field to [Manual], some fields will appear and selectable. 3-19 M S-7380 M ainboard CAS Latency(CL) W hen the Memory Timings sets to [Manual], the field is adjustable. This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. tRCD W hen the M emory Timings sets to [Manual], the field is adjustable. W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. tRP W hen the M emory Timings sets to [Manual], this field is adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. tRAS W hen the M emory Timings sets to [Manual], this field is adjustable. This setting determines the time RAS takes to read from and write to memory cell. tRRD W hen the Memory Timings sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. Time interval between a read and a precharge command. tRC W hen the M emory Timings sets to [Manual], the field is adjustable. The rowcycle time determines the minimum number of clock cycles a memory row takesto complete a full cycle, from row activation up to the precharging of the activerow. tWR W hen the Memory Timings sets to [Manual], the field is adjustable. Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. [. . . ] If you do not want to apply the adjustments, click the Cancel button to cancel. Or click the Default button to restore the default values. On the underside, it shows the graphs of the clocks. Only the curves of the item which the button is lit up with red color will be shown. Important In the user profile, clicking the Save button can save the changes to it. In the default profile, the Save button is not available. C-6 Dual Core Center Voltage In the Voltage sub-menu, you can see voltage status (including Vcore, memory, GPU voltage. . . [. . . ]