User manual OMRON CP PROGRAMMING MANUAL 05-2007

[. . . ] W451-E1-03 SYSMAC CP Series CP1H-X40D@-@, CP1H-XA40D@-@, CP1H-Y20DT-D CP1L-L14D@-@, CP1L-L20D@-@, CP1L-M30D@-@, CP1L-M40D@-@ CP1H/CP1L CPU Unit PROGRAMMING MANUAL SYSMAC CP Series CP1H-X40D@-@, CP1H-XA40D@-@, CP1H-Y20DT-D CP1H CPU Units CP1L-L14D@-@, CP1L-L20D@-@, CP1L-M30D@-@, CP1L-M40D@-@ CP1L CPU Units Programming Manual Revised May 2007 iv Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property. !DANGER !WARNING Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury. [. . . ] ON if the dividend and divisor are both 0. ON if the dividend and divisor are both + or ­. ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a double-precision floating-point value. ON if the absolute value of the result is too small to be expressed as a double-precision floating-point value. OFF in all other cases. Equals Flag Overflow Flag Underflow Flag Negative Flag = OF UF N Precautions The Dividend (Dd to Dd+3) and Divisor (Dr to Dr+3) data must be in IEEE754 floating-point data format. 543 Double-precision Floating-point Instructions Section 3-15 3-15-9 DOUBLE DEGREES TO RADIANS: RADD(849) Purpose Ladder Symbol RADD(849) Converts a double-precision (64-bit) floating-point number from degrees to radians and places the result in the specified result words. S D S: First source word D: First destination word Variations Variations Executed Each Cycle for ON Condition RADD(849) Executed Once for Upward Differentiation @RADD(849) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK Operand Specifications Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6140 W0 to W508 H0 to H508 A0 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764 @ D0 to @ D32767 *D0 to *D32767 ------, IR0 to , IR15 ­2048 to +2047 , IR0 to ­2048 to +2047 , IR15 DR0 to DR15, IR0 to IR15 , IR0+(++) to , IR15+(++) , ­(­ ­)IR0 to, ­(­ ­)IR15 A448 to A956 D Description RADD(849) converts the double-precision (64-bit) floating-point number in words S to S+3 from degrees to radians and places the result in words D to D+3. (The floating point source data must be in IEEE754 format. ) S+3 S+2 S+1 S Source (degrees, 64-bit floating-point data) D+3 D+2 D+1 D Result (radians, 64-bit floating-point data) Degrees are converted to radians by means of the following formula: Degrees × /180 = radians 544 Double-precision Floating-point Instructions Section 3-15 If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as ±. If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. Flags Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a double-precision floating-point value. ON if the absolute value of the result is too small to be expressed as a double-precision floating-point value. OFF in all other cases. Equals Flag Overflow Flag Underflow Flag Negative Flag = OF UF N Precautions The source data in words S to S+3 must be in IEEE754 floating-point data format. 3-15-10 DOUBLE RADIANS TO DEGREES: DEGD(850) Purpose Ladder Symbol DEGD(850) Converts a double-precision (64-bit) floating-point number from radians to degrees and places the result in the specified result words. S D S: First source word D: First destination word Variations Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation DEGD(850) @DEGD(850) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas OK Step program areas OK Subroutines OK Interrupt tasks OK Operand Specifications Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S CIO 0 to CIO 6140 W0 to W508 H0 to H508 A0 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764 A448 to A956 D 545 Double-precision Floating-point Instructions Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S @ D0 to @ D32767 *D0 to *D32767 ----- Section 3-15 D --, IR0 to , IR15 ­2048 to +2047 , IR0 to ­2048 to +2047 , IR15 DR0 to DR15, IR0 to IR15 , IR0+(++) to , IR15+(++) , ­(­ ­)IR0 to, ­(­ ­)IR15 Description DEGD(850) converts the double-precision (64-bit) floating-point number in words S to S+3 from radians to degrees and places the result in words D to D+3. (The floating point source data must be in IEEE754 format. ) S+3 S+2 S+1 S Source (radians, 64-bit floating-point data) D+3 D+2 D+1 D Result (degrees, 64-bit floating-point data) Radians are converted to degrees by means of the following formula: Radians × 180/ = degrees If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as ±. If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. Flags Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a double-precision floating-point value. [. . . ] For a CV/CVM1-series PLC, the immediate refresh variation of the MOVE instruction (!MOV) requires 4 words per instruction, so 7 steps (4 + 3) would be required for a CP-series PLC. Sequence Input Instructions Instruction Mnemonic Code Length (steps) (See note. ) 1 2 1 2 1 2 1 2 1 2 1 2 1 1 1 3 4 4 4 4 4 4 4 ON execution time (µs) CP1H CP1L 0. 10 0. 55 +24. 10 +5. 60 0. 10 0. 55 +24. 10 +5. 62 0. 10 0. 61 +24. 10 +5. 60 0. 10 0. 65 +24. 10 +5. 62 0. 10 0. 68 +24. 10 +5. 65 0. 10 0. 65 +24. 10 +5. 62 0. 05 0. 42 0. 05 0. 05 0. 50 0. 50 0. 35 0. 35 0. 35 0. 35 0. 35 0. 35 0. 39 0. 42 2. 37 2. 89 4. 22 4. 22 6. 50 4. 29 4. 31 4. 29 Conditions LOAD LOAD NOT AND AND NOT OR OR NOT AND LOAD OR LOAD NOT CONDITION ON CONDITION OFF LOAD BIT TEST LOAD BIT TEST NOT LD !LD LD NOT !LD NOT AND !AND AND NOT !AND NOT OR !OR OR NOT !OR NOT AND LD OR LD NOT UP DOWN LD TST LD TSTN ----------------------------520 521 522 350 351 350 351 350 351 --Increase for immediate refresh --Increase for immediate refresh --Increase for immediate refresh --Increase for immediate refresh --Increase for immediate refresh --Increase for immediate refresh ----------------------- AND BIT TEST AND TST AND BIT TEST NOT AND TSTN OR BIT TEST OR BIT TEST NOT OR TST OR TSTN Note When a double-length operand is used, add 1 to the value shown in the length column in the following table 1067 Instruction Execution Times and Number of Steps Sequence Output Instructions Instruction Mnemonic Code Length (steps) (See note. ) 1 2 1 2 1 2 2 1 2 1 2 4 4 2 3 2 3 2 3 ON execution time (µs) CP1H CP1L 0. 35 1. 10 +23. 07 +6. 05 0. 35 1. 07 +23. 07 +5. 94 0. 40 0. 50 0. 50 0. 30 5. 55 2. 37 2. 34 1. 40 Section 4-1 Conditions OUTPUT OUTPUT NOT KEEP DIFFERENTIATE UP DIFFERENTIATE DOWN SET RESET MULTIPLE BIT SET MULTIPLE BIT RESET SINGLE BIT SET OUT !OUT OUT NOT !OUT NOT KEEP DIFU DIFD SET !SET RSET !RSET SETA RSTA SETB --------11 13 14 --------530 531 532 533 534 --Increase for immediate refresh --Increase for immediate refresh --------Increase for immediate refresh Word specified Increase for immediate refresh With 1-bit set +23. 17 +7. 85 0. 30 1. 33 +23. 17 +7. 78 11. 77 16. 10 67. 03 11. 8 69. 63 0. 5 107. 50 With 1, 000-bit set 16. 11 With 1-bit reset 110. 70 With 1, 000-bit reset 25. 13 --- !SETB SINGLE BIT RESET RSTB SINGLE BIT OUTPUT !RSTB OUTB !OUTB +23. 31 +30. 88 --0. 5 25. 36 --+23. 31 +31. 11 --0. 45 27. 03 --+23. 22 +32. 68 --- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Sequence Control Instructions Instruction Mnemonic Code Length ON execution (steps) time (µs) (See CP1H CP1L note. ) 1 9. 18 6. 2 1 1 1 3 0. 05 0. 15 0. 15 10. 3 13. 3 16. 6 518 3 10. 3 13. 3 16. 6 8. 3 9. 6 0. 95 --0. 95 0. 6 3. 4 3. 4 11. 9 11. 9 10. 5 11. 9 11. 9 10. 5 6. 4 6. 4 4. 2 --6. 9 Conditions END NO OPERATION INTERLOCK END NOP IL 1 0 2 3 517 --------During interlock Not during interlock and interlock not set Not during interlock and interlock set During interlock Not during interlock and interlock not set Not during interlock and interlock set Interlock not cleared Interlock cleared ----When JMP condition is satisfied INTERLOCK CLEAR ILC MULTI-INTERLOCK MILH DIFFERENTIATION HOLD MULTI-INTERLOCK DIFFERENTIATION RELEASE MULTI-INTERLOCK CLEAR JUMP JUMP END CONDITIONAL JUMP MILR MILC JMP JME CJP 519 4 5 510 2 2 2 2 1068 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length ON execution (steps) time (µs) (See CP1H CP1L note. ) 2 0. 95 4. 3 1 1 2 1 1 0. 15 0. 15 1. 00 0. 15 0. 45 0. 55 1. 0 3. 4 6. 2 3. 4 4. 8 4. 8 Conditions Section 4-1 CONDITIONAL JUMP NOT MULTIPLE JUMP MULTIPLE JUMP END FOR LOOP BREAK LOOP NEXT LOOP CJPN JMP0 JME0 FOR BREAK NEXT 511 515 516 512 514 513 When JMP condition is satisfied ----Designating a constant --When loop is continued When loop is ended Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Timer and Counter Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 3 3 3 ON execution time (µs) CP1H CP1L 1. 30 1. 30 1. 80 1. 75 24. 81 17. 79 13. 97 23. 78 17. 76 14. 11 LONG TIMER TIML TIMLX MULTI-OUTPUT TIMER MTIM MTIMX REVERSIBLE COUNTER RESET TIMER/ COUNTER CNTR CNTRX CNR 542 553 543 554 12 548 545 3 3 4 4 15. 69 13. 61 17. 51 13. 11 35. 36 12. 81 41. 95 17. 42 29. 03 22. 44 15. 27 5. 95 ms 14. 44 5. 95 ms 6. 4 6. 7 6. 4 6. 4 12. 9 11. 7 10. 2 14. 2 11. 6 10. 1 13. 2 11. 5 14. 6 11. 2 14. 2 7. 6 27. 8 11. 5 14. 5 14. 3 10. 9 2. 70 ms 10. 9 2. 70 ms ----------When resetting When interlocking --When resetting When interlocking --When interlocking --When interlocking --When resetting --When resetting --When resetting 1 word When resetting 1, 000 words When resetting 1 word When resetting 1, 000 words Conditions TIMER COUNTER HIGH-SPEED TIMER ONE-MS TIMER ACCUMULATIVE TIMER TIM TIMX CNT CNTX TIMH TIMHX TMHH TMHHX TTIM --550 --546 15 551 540 552 87 TTIMX 555 CNRX 547 1069 Instruction Execution Times and Number of Steps Note Section 4-1 When a double-length operand is used, add 1 to the value shown in the length column in the following table. Comparison Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 0. 35 6. 0 --Conditions Input Comparison Instructions (unsigned) LD, AND, OR += LD, AND, OR + <> LD, AND, OR + < LD, AND, OR +<= LD, AND, OR +> LD, AND, OR +>= 300 305 310 315 320 325 Input Comparison Instructions (double, unsigned) LD, AND, OR +=+L 301 LD, AND, OR +<>+L 306 LD, AND, OR +<+L 311 LD, AND, OR +<=+L 316 LD, AND, OR +>+L 321 LD, AND, OR +>=+L 326 4 0. 35 6. 9 ------------- Input Comparison Instructions (signed) LD, AND, OR +=+S 302 LD, AND, OR +<>+S 307 LD, AND, OR +<+S 312 LD, AND, OR +<=+S 317 LD, AND, OR +>+S 322 LD, AND, OR +>=+S 327 4 0. 35 9. 8 --- Input Comparison Instructions (double, signed) LD, AND, OR +=+SL 303 LD, AND, OR 308 +<>+SL LD, AND, OR +<+SL 313 LD, AND, OR 318 +<=+SL LD, AND, OR +>+SL 323 LD, AND, OR +>=+SL 328 4 0. 35 10. 5 --- Time Comparison Instructions LD, AND, OR +DT 341 LD, AND, OR +<>DT 342 LD, AND, OR +<DT 343 LD, AND, OR +<=DT 344 LD, AND, OR +>DT 345 LD, AND, OR +>=DT 346 4 4 4 4 4 4 3 7 3 3 7 3 4 4 4 18. 8 45. 6 45. 6 18. 8 45. 6 18. 8 0. 10 +45. 2 0. 50 0. 30 +45. 2 0. 50 27. 66 42. 33 47. 21 53. 3 53. 3 53. 3 53. 2 53. 4 53. 1 4. 0 +17. 4 4. 8 11. 6 +32. 5 12. 5 32. 2 52. 4 45. 8 --------------Increase for immediate refresh ----Increase for immediate refresh --------- COMPARE CMP !CMP 20 20 60 114 114 115 85 19 68 DOUBLE COMPARE CMPL SIGNED BINARY CPS COMPARE !CPS DOUBLE SIGNED CPSL BINARY COMPARE TABLE COMPARE TCMP MULTIPLE COMPARE UNSIGNED BLOCK COMPARE MCMP BCMP 1070 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 3 3 ON execution time (µs) CP1H CP1L 13. 20 650. 0 11. 53 11. 28 18. 9 800. 7 13. 1 14. 4 Section 4-1 Conditions EXPANDED BLOCK BCMP2 COMPARE AREA RANGE COMPARE DOUBLE AREA RANGE COMPARE ZCP ZCPL 502 88 116 Number of data words: 1 Number of data words: 255 ----- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Data Movement Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 7 3 3 3 4 4 4 4 ON execution time (µs) CP1H CP1L 0. 30 4. 1 +35. 1 0. 60 0. 35 0. 60 0. 50 0. 50 +17. 3 4. 8 15. 5 16. 6 19. 4 22. 1 --Increase for immediate refresh ----------Transferring 1 bit Transferring 255 bits Transferring 1 word Transferring 1, 000 words Setting 1 word Setting 1, 000 words ------------Conditions MOVE DOUBLE MOVE MOVE NOT DOUBLE MOVE NOT MOVE BIT MOVE DIGIT MULTIPLE BIT TRANSFER MOV !MOV MOVL MVN MVNL MOVB MOVD XFRB 21 21 498 22 499 82 83 62 70 20. 1 19. 4 266. 30 252. 6 8. 80 1. 18 ms 14. 63 14. 9 1. 72 ms 14. 5 BLOCK TRANSFER XFER BLOCK SET DATA EXCHANGE DOUBLE DATA EXCHANGE SINGLE WORD DISTRIBUTE DATA COLLECT MOVE TO REGISTER MOVE TIMER/ COUNTER PV TO REGISTER BSET XCHG XCGL DIST COLL MOVR MOVRW 71 73 562 80 81 560 561 4 3 3 4 4 3 3 570. 17 549. 3 0. 80 20. 7 1. 5 12. 77 12. 85 0. 60 0. 60 22. 0 13. 8 11. 0 13. 8 13. 8 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Data Shift Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 ON execution time (µs) CP1H CP1L 12. 68 1. 49 ms 8. 8 2. 49 ms Conditions SHIFT REGISTER SFT 10 Shifting 1 word Shifting 1, 000 words 1071 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 13. 76 1. 54 ms 14. 21 2. 94 ms WSFT 16 4 11. 20 1. 47 ms 0. 45 0. 80 0. 45 0. 80 0. 45 0. 80 0. 45 0. 80 14. 0 2. 47 ms 14. 3 2. 49 ms 11. 6 3. 52 ms 21. 2 22. 0 19. 8 20. 4 25. 2 25. 7 23. 1 23. 6 Section 4-1 Conditions REVERSIBLE SHIFT REGISTER ASYNCHRONOUS SHIFT REGISTER WORD SHIFT SFTR 84 Shifting 1 word Shifting 1, 000 words Shifting 1 word Shifting 1, 000 words Shifting 1 word Shifting 1, 000 words ----------------- ASFT 17 4 ARITHMETIC SHIFT ASL LEFT DOUBLE SHIFT LEFT ASLL 25 570 26 571 27 572 574 576 2 2 2 2 2 2 2 2 ARITHMETIC SHIFT ASR RIGHT DOUBLE SHIFT ASRL RIGHT ROTATE LEFT ROL DOUBLE ROTATE LEFT ROTATE LEFT WITHOUT CARRY DOUBLE ROTATE LEFT WITHOUT CARRY ROTATE RIGHT DOUBLE ROTATE RIGHT ROTATE RIGHT WITHOUT CARRY DOUBLE ROTATE RIGHT WITHOUT CARRY ONE DIGIT SHIFT LEFT ONE DIGIT SHIFT RIGHT SHIFT N-BIT DATA LEFT SHIFT N-BIT DATA RIGHT ROLL RLNC RLNL ROR RORL RRNC RRNL 28 573 575 577 2 2 2 2 0. 45 0. 80 0. 45 0. 80 24. 7 25. 8 22. 4 23. 0 --------- SLD 74 3 11. 86 1. 24 ms 13. 95 1. 85 ms 12. 9 2. 51 ms 13. 1 3. 35 ms 14. 0 90. 5 Shifting 1 word Shifting 1, 000 words Shifting 1 word Shifting 1, 000 words Shifting 1 bit Shifting 1, 000 bits Shifting 1 bit Shifting 1, 000 bits --------- SRD 75 3 NSFL NSFR 578 579 580 582 581 583 4 4 3 3 3 3 14. 39 90. 10 14. 43 15. 5 130. 27 194. 1 0. 45 0. 80 0. 45 0. 80 27. 9 29. 2 27. 0 29. 0 SHIFT N-BITS LEFT NASL DOUBLE SHIFT N- NSLL BITS LEFT SHIFT N-BITS NASR RIGHT DOUBLE SHIFT NBITS RIGHT NSRL Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1072 Instruction Execution Times and Number of Steps Increment/Decrement Instructions Instruction Mnemonic Code Length (steps) (See note. ) 2 2 2 2 2 2 2 2 ON execution time (µs) CP1H CP1L 0. 45 0. 80 0. 45 0. 80 12. 09 10. 59 11. 63 9. 59 19. 1 23. 8 23. 2 23. 6 10. 2 10. 6 11. 9 10. 6 ----------------- Section 4-1 Conditions INCREMENT BINARY DOUBLE INCREMENT BINARY DECREMENT BINARY DOUBLE DECREMENT BINARY INCREMENT BCD DOUBLE INCREMENT BCD DECREMENT BCD DOUBLE DECREMENT BCD ++ ++L ­­ ­ ­L ++B ++BL ­ ­B ­ ­BL 590 591 592 593 594 595 596 597 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Symbol Math Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 4 ON execution time (µs) CP1H CP1L 0. 30 14. 1 0. 60 15. 3 ----Conditions SIGNED BINARY ADD WITHOUT CARRY DOUBLE SIGNED BINARY ADD WITHOUT CARRY SIGNED BINARY ADD WITH CARRY DOUBLE SIGNED BINARY ADD WITH CARRY BCD ADD WITHOUT CARRY DOUBLE BCD ADD WITHOUT CARRY BCD ADD WITH CARRY DOUBLE BCD ADD WITH CARRY SIGNED BINARY SUBTRACT WITHOUT CARRY DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY SIGNED BINARY SUBTRACT WITH CARRY DOUBLE SIGNED BINARY SUBTRACT WITH CARRY BCD SUBTRACT WITHOUT CARRY + +L 400 401 +C +CL 402 403 4 4 0. 40 0. 60 14. 2 15. 5 ----- +B +BL +BC +BCL ­ 404 405 406 407 410 4 4 4 4 4 18. 14 22. 87 19. 7 23. 63 0. 3 16. 3 20. 1 16. 4 20. 2 14. 1 ----------- ­L 411 4 0. 60 15. 4 --- ­C 412 4 0. 40 14. 2 --- ­CL 413 4 0. 60 15. 5 --- ­B 414 4 17. 57 16. 2 --- 1073 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 22. 09 19. 9 --- Section 4-1 Conditions DOUBLE BCD SUBTRACT WITHOUT CARRY BCD SUBTRACT WITH CARRY DOUBLE BCD SUBTRACT WITH CARRY SIGNED BINARY MULTIPLY DOUBLE SIGNED BINARY MULTIPLY UNSIGNED BINARY MULTIPLY DOUBLE UNSIGNED BINARY MULTIPLY BCD MULTIPLY DOUBLE BCD MULTIPLY ­BL 415 ­BC ­BCL 416 417 4 4 18. 37 22. 91 16. 3 20. 1 ----- * *L *U *UL *B *BL 420 421 422 423 424 425 430 431 432 433 434 435 4 4 4 4 4 4 4 4 4 4 4 4 0. 65 13. 02 0. 75 13. 23 16. 83 33. 33 0. 70 13. 35 0. 8 12. 91 18. 03 27. 77 27. 2 16. 9 27. 2 16. 8 17. 4 29. 4 37. 4 17. 2 36. 5 17. 1 18. 6 25. 3 ------------------------- SIGNED BINARY DIVIDE / DOUBLE SIGNED /L BINARY DIVIDE UNSIGNED BINARY /U DIVIDE DOUBLE UNSIGNED BINARY DIVIDE BCD DIVIDE DOUBLE BCD DIVIDE /UL /B /BL Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Conversion Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 3 3 3 3 3 4 ON execution time (µs) CP1H 0. 40 10. 41 10. 22 10. 18 0. 35 0. 60 0. 60 12. 09 14. 15 24. 01 37. 72 CP1L 57. 5 14. 1 12. 8 14. 2 22. 8 24. 4 25. 5 15. 1 15. 0 43. 1 76. 9 --------------Decoding 1 digit (4 to 16) Decoding 4 digits (4 to 16) Decoding 1 digit 8 to 256 Decoding 2 digits (8 to 256) Conditions BCD-TO-BINARY DOUBLE BCD-TODOUBLE BINARY BINARY-TO-BCD DOUBLE BINARYTO-DOUBLE BCD 2'S COMPLEMENT DOUBLE 2'S COMPLEMENT 16-BIT TO 32-BIT SIGNED BINARY DATA DECODER BIN BINL BCD BCDL NEG NEGL SIGN MLPX 023 058 024 059 160 161 600 076 1074 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 11. 90 58. 70 19. 76 80. 32 ASCII CONVERT ASCII TO HEX COLUMN TO LINE LINE TO COLUMN SIGNED BCD-TOBINARY ASC HEX LINE COLM BINS 086 162 063 064 470 4 4 4 4 4 12. 49 18. 03 12. 64 34. 95 42. 09 15. 73 15. 93 15. 93 BISL 472 4 16. 00 18. 59 18. 66 18. 41 BCDS 471 4 18. 47 13. 16 13. 18 13. 00 BDSL 473 4 13. 12 13. 74 13. 58 13. 79 13. 75 GRAY CODE CONVERSION GRY 474 4 82. 99 81. 67 98. 65 97. 67 14. 4 24. 1 16. 9 16. 9 12. 1 20. 0 15. 6 28. 4 40. 4 15. 7 15. 7 15. 9 16. 0 17. 4 17. 5 17. 7 17. 7 17. 4 17. 5 17. 7 17. 7 16. 3 16. 4 16. 5 16. 6 78. 2 80. 6 90. 4 100. 5 Section 4-1 Conditions DATA ENCODER DMPX 077 Encoding 1 digit (16 to 4) Encoding 4 digits (16 to 4) Encoding 1 digit (256 to 8) Encoding 2 digits (256 to 8) Converting 1 digit into ASCII Converting 4 digits into ASCII Converting 1 digit ----Data format setting No. 3 8-bit binary 8-bit BCD 8-bit angle 15-bit binary 15-bit BCD 15-bit angle 360° binary 360° BCD 360° angle DOUBLE SIGNED BCD-TO-BINARY SIGNED BINARYTO-BCD DOUBLE SIGNED BINARY-TO-BCD 98. 99 114. 5 110. 67 112. 9 97. 00 93. 7 108. 33 99. 7 113. 00 92. 3 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Logic Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 4 4 4 4 4 ON execution time (µs) CP1H CP1L 0. 30 0. 60 0. 45 0. 60 0. 45 0. 60 27. 0 28. 3 27. 3 27. 3 26. 6 27. 6 ------------Conditions LOGICAL AND DOUBLE LOGICAL AND LOGICAL OR DOUBLE LOGICAL OR EXCLUSIVE OR DOUBLE EXCLUSIVE OR ANDW ANDL ORW ORWL XORW XORL 034 610 035 611 036 612 1075 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 4 2 2 ON execution time (µs) CP1H CP1L 0. 45 0. 60 0. 45 0. 80 27. 1 28. 5 22. 1 22. 5 --------- Section 4-1 Conditions EXCLUSIVE NOR DOUBLE EXCLUSIVE NOR COMPLEMENT DOUBLE COMPLEMENT XNRW XNRL COM COML 037 613 029 614 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Special Math Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 4 4 4 ON execution time (µs) CP1H 43. 99 49. 32 13. 96 30. 51 CP1L 44. 3 43. 6 20. 4 27. 2 ----Designating SIN and COS Designating line-segment approximation --Counting 1 word Conditions BINARY ROOT BCD SQUARE ROOT ARITHMETIC PROCESS FLOATING POINT DIVIDE BIT COUNTER ROTB ROOT APR FDIV BCNT 620 072 069 079 067 222. 90 169. 6 29. 70 43. 5 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1076 Instruction Execution Times and Number of Steps Floating-point Math Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 3 3 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 4 3 ON execution time (µs) CP1H CP1L 13. 03 12. 03 8. 97 9. 92 12. 60 12. 70 13. 40 12. 67 15. 00 17. 97 37. 10 41. 97 30. 86 65. 14 31. 26 53. 07 20. 73 53. 07 50. 08 185. 77 11. 01 14. 4 14. 9 14. 0 14. 4 14. 3 14. 4 14. 4 13. 5 19. 7 17. 3 38. 4 39. 8 46. 7 59. 0 22. 7 34. 1 22. 7 55. 0 49. 1 104. 3 13. 0 ------------------------------------------- Section 4-1 Conditions FLOATING TO 16-BIT FLOATING TO 32-BIT 16-BIT TO FLOATING 32-BIT TO FLOATING FLOATING-POINT ADD FLOATING-POINT SUBTRACT FLOATING-POINT DIVIDE FLOATING-POINT MULTIPLY DEGREES TO RADIANS RADIANS TO DEGREES SINE COSINE TANGENT ARC SINE ARC COSINE ARC TANGENT SQUARE ROOT EXPONENT LOGARITHM EXPONENTIAL POWER Floating Symbol Comparison FIX FIXL FLT FLTL +F ­F 450 451 452 453 454 455 457 456 458 459 460 461 462 463 464 465 466 467 468 840 329 330 331 332 333 334 448 449 /F *F RAD DEG SIN COS TAN ASIN ACOS ATAN SQRT EXP LOG PWR LD, AND, OR +=F LD, AND, OR +<>F LD, AND, OR +<F LD, AND, OR +<=F LD, AND, OR +>F LD, AND, OR +>=F FLOATING- POINT TO ASCII FSTR ASCII TO FLOATING-POINT FVAL 4 3 46. 57 25. 37 49. 0 27. 7 ----- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Double-precision Floating-point Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 ON execution time (µs) CP1H CP1L 16. 04 17. 0 --Conditions DOUBLE SYMBOL COMPARISON LD, AND, OR +=D LD, AND, OR +<>D LD, AND, OR +<D LD, AND, OR +<=D LD, AND, OR +>D LD, AND, OR +>=D 335 336 337 338 339 340 841 842 DOUBLE FLOATING TO 16BIT BINARY DOUBLE FLOATING TO 32BIT BINARY FIXD FIXLD 3 3 15. 63 14. 90 18. 4 18. 8 ----- 1077 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 3 3 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 4 ON execution time (µs) CP1H CP1L 12. 29 14. 13 17. 89 17. 96 17. 96 37. 09 32. 07 33. 76 66. 97 55. 89 85. 56 22. 64 15. 64 14. 91 16. 0 16. 5 23. 5 22. 9 24. 1 32. 5 31. 3 31. 1 64. 2 41. 4 85. 3 26. 6 28. 6 24. 6 ------------------------------------- Section 4-1 Conditions 16-BIT BINARY TO DOUBLE FLOATING 32-BIT BINARY TO DOUBLE FLOATING DOUBLE FLOATING-POINT ADD DOUBLE FLOATING-POINT SUBTRACT DOUBLE FLOATING-POINT MULTIPLY DOUBLE FLOATING-POINT DIVIDE DOUBLE DEGREES TO RADIANS DOUBLE RADIANS TO DEGREES DOUBLE SINE DOUBLE COSINE DOUBLE TANGENT DOUBLE ARC SINE DOUBLE ARC COSINE DOUBLE ARC TANGENT DOUBLE SQUARE ROOT DOUBLE EXPONENT DOUBLE LOGARITHM DOUBLE EXPONENTIAL POWER DBL DBLL +D -D *D /D RADD DEGD SIND COSD TAND ASIND ACOSD ATAND SQRTD EXPD LOGD PWRD 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 46. 97 45. 5 102. 49 97. 5 19. 03 22. 3 182. 83 183. 0 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Table Data Processing Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 3 ON execution time (µs) CP1H CP1L Designating 5 words in stack area Designating 1, 000 words in stack area --Designating 5 words in stack area Designating 1, 000 words in stack area --------Searching for 1 word Searching for 1, 000 words 16. 97 17. 6 700. 67 1200 14. 20 11. 50 1. 48 ms 16. 94 30. 69 12. 82 15. 78 29. 11 4. 86 ms 10. 8 9. 7 1. 80 ms 11. 4 33. 6 10. 7 12. 7 41. 6 5. 12 ms Conditions SET STACK SSET 630 632 633 PUSH ONTO STACK PUSH FIFO FIRST IN FIRST OUT LAST IN FIRST OUT LIFO DIMENSION RECORD TABLE SET RECORD LOCATION GET RECORD NUMBER DATA SEARCH DIM SETR GETR SRCH 634 631 635 636 181 3 5 4 4 4 1078 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 3 ON execution time (µs) CP1H CP1L 22. 67 3. 79 ms 34. 17 4. 46 ms FIND MINIMUM MIN 183 4 34. 97 4. 74 ms 46. 63 2. 37 ms 33. 17 3. 30 ms SNUM SREAD SWRIT SINS SDEL 638 639 640 641 642 3 4 4 4 4 12. 21 14. 24 13. 20 17. 78 27. 8 6. 50 ms 44. 6 6. 01 ms 44. 5 5. 98 ms 49. 3 2. 95 ms 41. 1 4. 15 ms 9. 6 12. 5 12. 3 13. 8 Section 4-1 Conditions SWAP BYTES SWAP 637 Swapping 1 word Swapping 1, 000 words Searching for 1 word Searching for 1, 000 words Searching for 1 word Searching for 1, 000 words Adding 1 word Adding 1, 000 words For 1-word table length For 1, 000-word table length --------For 1, 000-word table --For 1, 000-word table FIND MAXIMUM MAX 182 4 SUM SUM 184 4 FRAME CHECKSUM STACK SIZE READ STACK DATA READ STACK DATA OVERWRITE STACK DATA INSERT STACK DATA DELETE FCS 180 4 758. 04 480. 1 19. 83 16. 0 763. 61 471. 8 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Data Control Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 550. 12 237. 9 546. 43 672. 9 152. 87 308. 3 LIMIT CONTROL DEAD BAND CONTROL DEAD ZONE CONTROL TIMEPROPORTIONAL OUTPUT LMT BAND ZONE TPO 680 681 682 685 4 4 4 4 27. 1 27. 23 26. 43 19. 85 86. 03 95. 27 32. 3 33. 2 32. 6 117. 1 103. 0 100. 3 Conditions PID CONTROL PID 190 Initial execution Sampling Not sampling ------OFF execution time ON execution time with duty designation or displayed output limit ON execution time with manipulated variable designation and output limit enabled ------- SCALING SCALING 2 SCALING 3 SCL SCL2 SCL3 194 486 487 4 4 4 23. 30 20. 93 24. 37 22. 0 16. 4 21. 4 1079 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 4 ON execution time (µs) CP1H CP1L 63. 4 70. 1 540. 87 725. 3 740. 97 462. 7 611. 30 488. 3 197. 97 837. 2 212. 86 693. 6 548. 97 329. 2 Section 4-1 Conditions AVERAGE AVG 195 191 Average of an operation Average of 64 operations Initial execution Sampling Not sampling Initial execution of autotuning Autotuning when sampling PID CONTROL PIDAT WITH AUTOTUNING Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Subroutine Instructions Instruction Mnemonic Code Length (steps) (See note. ) 2 2 1 4 2 1 2 ON execution time (µs) CP1H CP1L 2. 04 --1. 80 47. 9 --2. 04 1. 80 2. 9 --8. 0 45. 2 --7. 9 2. 9 --------------Conditions SUBROUTINE CALL SUBROUTINE ENTRY SUBROUTINE RETURN MACRO GLOBAL SUBROUTINE CALL GLOBAL SUBROUTINE ENTRY SBS SBN RET MCRO GSBN GRET 91 92 93 99 751 752 750 GLOBAL SUBROUTINE RETURN GSBS Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Interrupt Control Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 3 3 1 1 ON execution time (µs) CP1H 51. 90 63. 09 19. 99 43. 67 49. 46 38. 93 14. 83 27. 44 CP1L 46. 4 77. 5 27. 4 52. 0 52. 7 43. 8 21. 0 13. 1 Set Reset Set Reset Set Reset ----Conditions SET INTERRUPT MASK READ INTERRUPT MASK CLEAR INTERRUPT DISABLE INTERRUPTS ENABLE INTERRUPTS MSKS MSKR CLI DI EI 690 692 691 693 694 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1080 Instruction Execution Times and Number of Steps High-speed Counter and Pulse Output Instructions Instruction Mnemonic Code Length ON execution (steps) time (µs) (See CP1H CP1L note. ) 4 80. 39 85. 5 47. 99 47. 99 48. 01 27. 92 48. 45 26. 08 ----HIGH-SPEED COUNTER PV READ PRV 881 4 80. 39 40. 92 28. 63 39. 20 66. 43 34. 63 55. 0 67. 6 30. 0 36. 4 63. 0 37. 8 95. 2 104. 7 55. 2 79. 2 38. 0 48. 6 78. 9 43. 7 Conditions Section 4-1 MODE CONTROL INI 880 Starting high-speed counter comparison Stopping high-speed counter comparison Changing pulse output PV Changing high-speed counter PV Changing PV of counter in interrupt input mode Stopping pulse output Stopping PWM(891) output Changing PV of inverter positioning Stopping inverter positioning Reading pulse output PV Reading high-speed counter PV Reading high-speed counter status Reading pulse output status Reading high-speed counter status Reading PWM(891) status Reading high-speed counter range comparison results Reading frequency of high-speed counter 0 Reading PV of inverter positioning Reading status of inverter positioning --- 145. 52 108. 8 47. 48 --COUNTER FREQUENCY CONVERT COMPARISON TABLE LOAD PRV2 883 4 --20. 03 68. 6 51. 8 48. 0 28. 3 CTBL 882 4 221. 63 225. 3 9. 578 8. 08 ms ms 262. 37 261. 5 166. 03 176. 9 9. 557 ms 8. 04 ms Registering target value table and starting comparison for 1 target value Registering target value table and starting comparison for 48 target values Registering range table and starting comparison Only registering target value table for 1 target value Only registering target value table for 48 target values Only registering range table Continuous mode Independent mode ----Continuous mode Independent mode Origin search Origin return --- SPEED OUTPUT SET PULSES PULSE OUTPUT ACCELERATION CONTROL ORIGIN SEARCH PULSE WITH VARIABLE DUTY FACTOR SPED PULS PLS2 ACC ORG PWM 885 886 887 888 889 891 4 4 5 4 3 4 241. 70 235. 8 89. 24 105. 2 94. 47 32. 63 109. 3 36. 0 103. 19 15. 6 111. 26 119. 1 121. 73 130. 9 112. 93 114. 6 98. 65 30. 26 113. 4 21. 9 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1081 Instruction Execution Times and Number of Steps Step Instructions Instruction Mnemonic Code Length (steps) (See note. ) 2 2 ON execution time (µs) CP1H CP1L 36. 10 18. 77 10. 35 15. 0 24. 4 8. 6 Section 4-1 Conditions STEP DEFINE STEP START STEP SNXT 008 009 Step control bit ON Step control bit OFF --- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. I/O Unit Instructions Instruction Mnemonic Code Length ON execution (steps) time (µs) (See CP1H CP1L note. ) 3 119. 50 109. 7 122. 17 100. 1 282. 20 --390. 50 --1. 58 ms 1. 50 ms 720. 83 1. 032 ms 12. 53 85. 43 80. 43 82. 11 75. 23 17. 49 18. 69 72. 77 75. 63 71. 55 79. 77 88. 23 86. 97 232. 10 237. 10 229. 57 261. 10 259. 10 259. 77 425. 69 1. 18 ms 1. 09 ms ----99. 8 93. 7 86. 3 78. 7 87. 3 25. 3 23. 7 79. 2 77. 1 83. 1 88. 6 112. 5 101. 1 --------------Conditions I/O REFRESH IORF 097 Refreshing 1 input word for CPM1A Unit Refreshing 1 output word for CPM1A Unit Refreshing 1 input word for CJ-series Special I/O Unit Refreshing 1 output word for CJ-series Special I/O Unit Refreshing 10 input words for CPM1A Unit Refreshing 10 output words for CPM1A Unit Refreshing 60 input words for CJ-series Special I/O Unit Refreshing 60 output words for CJ-series Special I/O Unit --4 digits, data input value: 0 4 digits, data input value: F 8 digits, data input value: 0 8 digits, data input value: F Data input value: 0 Data input value: F Data input value: 0 Data input value: F Data input value: 0 Data input value: F 4 digits 8 digits First execution When busy At end First execution When busy At end Allocated 1 word 7-SEGMENT DECODER DIGITAL SWITCH INPUT SDEC DSW 078 210 4 6 TEN KEY INPUT HEXADECIMAL KEY INPUT MATRIX INPUT 7-SEGMENT DISPLAY OUTPUT INTELLIGENT I/O READ INTELLIGENT I/O WRITE CPU BUS I/O REFRESH TKY HKY MTR 7SEG IORD 211 212 213 214 222 4 5 5 5 4 IOWR 223 4 DLNK 226 4 Note (1) When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1082 Instruction Execution Times and Number of Steps Section 4-1 (2) The execution times of IORD(222) and IOWR(223) depend on the Special I/O Unit for which the instruction is executed. Serial Communications Instructions Instruction Mnemonic Code Length ON execution (steps) time (µs) (See CP1H CP1L note. ) 5 152. 83 --186. 37 --4 107. 67 118. 2 1. 22 1. 31 ms ms 4 149. 3 160. 0 1. 33 1. 45 ms ms 4 145. 64 --Conditions PROTOCOL MACRO TRANSMIT PMCR TXD 260 236 Sending 0 words, receiving 0 words Sending 249 words, receiving 249 words Sending 1 byte Sending 256 bytes Storing 1 byte Storing 256 bytes Sending 1 byte RECEIVE RXD 235 TRANSMIT VIA TXDU SERIAL COMMUNICATIONS UNIT RECEIVE VIA RXDU SERIAL COMMUNICATIONS UNIT CHANGE SERIAL STUP PORT SETUP 256 255 4 44. 48 --- Storing 1 byte 237 3 479. 3 252. 8 --- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Network Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 4 4 4 4 3 4 4 ON execution time (µs) CP1H CP1L 174. 63 158. 4 173. 97 153. 8 195. 97 186. 3 228. 63 --203. 30 --197. 30 --188. 63 --181. 97 --Conditions NETWORK SEND NETWORK RECEIVE DELIVER COMMAND EXPLICIT MESSAGE SEND EXPLICIT GET ATTRIBUTE EXPLICIT SET ATTRIBUTE EXPLICIT WORD READ EXPLICIT WORD WRITE SEND RECV CMND EXPLT EGATR ESATR ECHRD ECHWR 090 098 490 720 721 722 723 724 ----------------- Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Code Length (steps) (See note. ) 3 3 ON execution time (µs) CP1H CP1L 17. 16 22. 6 15. 43 22. 6 48. 13 --Conditions Display Instructions Instruction Mnemonic DISPLAY MESSAGE MSG 7-SEGMENT LED WORD DATA DISPLAY 7-SEGMENT LED CONTROL SCH 046 047 Displaying message Deleting displayed message --- SCTRL 048 2 36. 40 --- --- 1083 Instruction Execution Times and Number of Steps Note Section 4-1 When a double-length operand is used, add 1 to the value shown in the length column in the following table. Clock Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 4 3 3 2 ON execution time (µs) CP1H CP1L 212. 90 219. 9 176. 23 223. 3 34. 19 40. 95 37. 0 44. 1 ----------Conditions CALENDAR ADD CADD CALENDAR SUBTRACT CSUB HOURS TO SECONDS SECONDS TO HOURS CLOCK ADJUSTMENT SEC HMS DATE 730 731 065 066 735 134. 67 123. 7 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Debugging Instructions Instruction Mnemonic Code Length (steps) (See note. ) 1 ON execution time (µs) CP1H 201. 33 1. 12 ms CP1L 30. 3 158. 7 Conditions TRACE MEMORY SAMPLING TRSM 045 Sampling 1 bit and 0 words Sampling 31 bits and 6 words Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Failure Diagnosis Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 ON execution time (µs) CP1H CP1L 23. 24 27. 3 266. 57 406. 7 817. 17 610. 7 SEVERE FAILURE ALARM FAILURE POINT DETECTION FALS FPD 007 269 3 4 305. 33 410. 0 ----245. 07 286. 7 258. 2 362. 4 317. 73 363. 1 316. 4 400 Conditions FAILURE ALARM FAL 006 Recording errors Deleting errors (in order of priority) Deleting errors (all errors) Deleting errors (individually) --When executed First time When executed First time Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1084 Instruction Execution Times and Number of Steps Other Instructions Instruction Mnemonic Code Length (steps) (See note. ) 1 1 2 1 1 3 3 ON execution time (µs) CP1H CP1L 0. 15 0. 15 23. 94 14. 97 17. 83 31. 03 34. 90 10. 0 10. 2 24. 2 17. 5 18. 9 29. 1 28. 0 --------------- Section 4-1 Conditions SET CARRY CLEAR CARRY EXTEND MAXIMUM CYCLE TIME SAVE CONDITION FLAGS LOAD CONDITION FLAGS CONVERT ADDRESS FROM CV CONVERT ADDRESS TO CV STC CLC WDT CCS CCL FRMCV TOCV 040 041 094 282 283 284 285 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Block Programming Instructions Instruction Mnemonic Code Length (steps) (See note. ) 2 1 2 2 1 2 2 1 2 2 1 1 1 2 2 ON execution time (µs) CP1H CP1L 26. 59 24. 19 18. 13 9. 29 23. 33 9. 33 26. 78 11. 47 26. 74 11. 41 7. 4 13. 5 11. 55 13. 55 11. 61 13. 61 7. 71 13. 55 13. 58 7. 49 27. 53 6. 15 28. 78 9. 82 26. 27 9. 78 9. 2 6. 4 7. 2 6. 8 8. 0 5. 8 10. 8 8. 4 9. 0 11. 2 4. 0 6. 6 7. 6 10. 2 10. 6 8. 0 6. 0 4. 2 4. 6 6. 1 3. 7 9. 3 7. 4 10. 8 11. 2 7. 8 --------EXIT condition satisfied EXIT condition not satisfied EXIT condition satisfied EXIT condition not satisfied EXIT condition satisfied EXIT condition not satisfied IF true IF false IF true IF false IF true IF false IF true IF false IF true IF false WAIT condition satisfied WAIT condition not satisfied WAIT condition satisfied WAIT condition not satisfied WAIT condition satisfied WAIT condition not satisfied Conditions BLOCK PROGRAM BEGIN BLOCK PROGRAM END BLOCK PROGRAM PAUSE BLOCK PROGRAM RESTART CONDITIONAL BLOCK EXIT CONDITIONAL BLOCK EXIT CONDITIONAL BLOCK EXIT (NOT) Branching Branching Branching (NOT) Branching Branching ONE CYCLE AND WAIT ONE CYCLE AND WAIT ONE CYCLE AND WAIT (NOT) BPRG BEND BPPS BPRS (Execution condition) EXIT EXIT (bit address) EXIT NOT (bit address) IF (execution condition) IF (relay number) IF NOT (relay number) ELSE IEND WAIT (execution condition) WAIT (relay number) WAIT NOT (relay number) 096 801 811 812 806 806 806 802 802 802 803 804 805 805 805 1085 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 4 3 3 1 1 2 2 3 3 ON execution time (µs) CP1H CP1L 36. 57 36. 40 43. 69 36. 95 48. 37 48. 20 50. 59 45. 52 17. 03 17. 13 18. 07 20. 77 23. 63 23. 43 20. 97 48. 40 46. 33 48. 02 47. 09 17. 6 16. 2 18. 1 14. 8 21. 4 14. 0 19. 6 13. 6 6. 3 6. 5 6. 0 9. 5 9. 2 9. 9 9. 5 19. 5 13. 6 19. 4 13. 5 Section 4-1 Conditions COUNTER WAIT CNTW CNTWX 814 818 815 817 809 810 810 810 813 816 First execution Normal execution First execution Normal execution First execution Normal execution First execution Normal execution --LEND condition satisfied LEND condition not satisfied LEND condition satisfied LEND condition not satisfied LEND condition satisfied LEND condition not satisfied Default setting Normal execution Default setting Normal execution HIGH-SPEED TIMER WAIT TMHW TMHWX Loop Control Loop Control Loop Control Loop Control TIMER WAIT LOOP LEND (execution condition) LEND (relay number) LEND NOT (relay number) TIMW TIMWX Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Text String Processing Instructions Instruction Mnemonic Code Length (steps) (See note. ) 3 4 4 4 5 4 3 6 5 3 2 5 ON execution time (µs) CP1H CP1L 68. 44 78. 9 145. 10 146. 0 87. 81 91. 81 94. 77 82. 81 94. 7 95. 4 97. 2 99. 1 Conditions MOV STRING CONCATENATE STRING GET STRING LEFT GET STRING RIGHT GET STRING MIDDLE FIND IN STRING STRING LENGTH REPLACE IN STRING DELETE STRING EXCHANGE STRING CLEAR STRING INSERT INTO STRING MOV$ +$ LEFT$ RGHT$ MID$ FIND$ LEN$ RPLC$ DEL$ XCHG$ CLR$ INS$ 664 656 652 653 654 660 650 661 658 665 666 657 Transferring 1 character 1 character + 1 character Retrieving 1 character from 2 characters Retrieving 1 character from 2 characters Retrieving 1 character from 3 characters Searching for 1 character from 2 characters Detecting 1 character Replacing the first of 2 characters with 1 character Deleting the leading character of 2 characters Exchanging 1 character with 1 character Clearing 1 character Inserting 1 character after the first of 2 characters 32. 61 38. 4 269. 43 289. 7 114. 00 254. 5 108. 54 138. 7 37. 33 39. 3 199. 43 253. 3 1086 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 64. 47 63. 6 Section 4-1 Conditions String Comparison Instructions LD, AND, OR +=$ LD, AND, OR +<>$ LD, AND, OR +<$ LD, AND, OR +<=$ LD, AND, OR +>$ LD, AND, OR +>=$ 670 671 672 673 674 675 Comparing 1 character with 1 character Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Task Control Instructions Instruction Mnemonic Code Length (steps) (See note. ) 2 2 ON execution time (µs) CP1H CP1L 30. 65 23. 2 18. 30 23. 4 ----Conditions TASK ON TASK OFF TKON TKOF 820 821 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Model Conversion Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H 37. 04 2. 922 ms SINGLE WORD DISTRIBUTE DATA COLLECT DISTC COLLC 566 567 4 4 24. 80 35. 57 29. 83 30. 13 31. 10 8. 100 ms 28. 03 32. 97 5. 703 ms CP1L 24. 5 4. 65 ms 34. 9 45. 0 36. 6 39. 2 39. 2 14. 7 ms 34. 9 41. 5 6. 09 ms Conditions BLOCK TRANSFER XFERC 565 Transferring 1 word Transferring 1, 000 words Data distribute Stack operation Data distribute Stack operation Stack operation 1 word FIFO Read Stack operation 1, 000 word FIFO Read --Counting 1 word Counting 1, 000 words MOVE BIT BIT COUNTER MOVBC BCNTC 568 621 4 4 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. Special Function Block Instructions Instruction Mnemonic Code Length (steps) (See note. ) 4 ON execution time (µs) CP1H CP1L 26. 5 32. 8 --Conditions GET VARIABLE ID GETID 286 Note When a double-length operand is used, add 1 to the value shown in the length column in the following table. 1087 Function Block Instance Execution Time Section 4-2 4-2 Function Block Instance Execution Time Use the following equation to calculate the effect of instance execution on the cycle time when function block definitions have been created and the instances copied into the user program. Effect of Instance Execution on Cycle Time = Startup time (A) + I/O parameter transfer processing time (B) + Execution time of instructions in function block definition (C) The following table shows the length of time for A, B, and C. Operation A B Startup time I/O parameter transfer processing time The data type is indicated in parentheses. Startup time not including I/O parameter transfer 1-bit I/O variable (BOOL) 1-word I/O variable (INT, UINT, WORD) 2-word I/O variable (DINT, UDINT, DWORD, REAL) 4-word I/O variable (LINT, ULINT, LWORD, LREAL) CP1H CPU Unit 6. 8 µs 0. 4 µs 0. 3 µs 0. 5 µs 1. 0 µs CP1L CPU Unit 320. 4 µs 59. 52 µs 13. 16 µs 15. 08 µs 30. 16 µs C Function block definition Total instruction processing time (same as standard user program) instruction execution time Example: Input variables with a 1-word data type (INT): 3 Output variables with a 1-word data type (INT): 2 Total instruction processing time in function block definition section: 10 µs Execution time for 1 instance = 6. 8 µs + (3 + 2) × 0. 3 µs + 10 µs = 18. 3 µs Note Number of Function Block Program Steps The execution time is increased according to the number of multiple instances when the same function block definition has been copied to multiple locations. Use the following equation to calculate the number of program steps when function block definitions have been created and the instances copied into the user program. Number of steps = Number of instances × (Call part size m + I/O parameter transfer part size n × Number of parameters) + Number of instruction steps in the function block definition p (See note. ) Note The number of instruction steps in the function block definition (p) will not be diminished in subsequence instances when the same function block definition is copied to multiple locations (i. e. , for multiple instances). [. . . ]