User manual TEXAS INSTRUMENTS STELLARIS LM3S1110 DATA SHEET REV D

[. . . ] TE X AS INS TRUM E NTS - P RO DUCTI O N D ATA Stellaris® LM3S1110 Microcontroller D ATA SHE E T D S -LM 3S 1110 - 7 3 9 3 C opyri ght © 2007-2010 Texas Instr uments Incor porated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. [. . . ] However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 8. 2. 2. 2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in one pair of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 8-1 on page 138. Flash Protection Policy Combinations FMPPEn 0 1 FMPREn 0 0 Protection Execute-only protection. The block may only be executed and may not be written or erased. The block may be written, erased or executed, but not read. This combination is unlikely to be used. 138 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1110 Microcontroller Table 8-1. Flash Protection Policy Combinations (continued) FMPPEn 0 FMPREn 1 Protection Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. The block may be written, erased, executed or read. 1 1 A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]