User manual TEXAS INSTRUMENTS STELLARIS LM3S1110 MICROCONTROLLER DATASHEET

[. . . ] TE X AS INS TRUM E NTS - P RO DUCTI O N D ATA Stellaris® LM3S1110 Microcontroller D ATA SHE E T D S -LM 3S 1110 - 7 7 8 7 C opyri ght © 2007-2010 Texas Instr uments Incor porated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. [. . . ] Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 0 MOSCDIS R/W 1 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). September 04, 2010 Texas Instruments-Production Data 183 System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 181). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F. E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 F RO RO RO RO RO RO RO RO RO RO RO RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 R RO RO RO RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL's F input. 13:5 F RO - 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL's R input. 184 Texas Instruments-Production Data September 04, 2010 Stellaris® LM3S1110 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-5, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. RCC2 Fields that Override RCC fields RCC2 Field. . . SYSDIV2, bits[28:23] PWRDN2, bit[13] BYPASS2, bit[11] OSCSRC2, bits[6:4] Overrides RCC Field SYSDIV, bits[26:23] PWRDN, bit[13] BYPASS, bit[11] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F. E000 Offset 0x070 Type R/W, reset 0x0780. 2810 31 USERCC2 Type Reset R/W 0 15 30 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 reserved RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 7 RO 0 6 RO 0 5 OSCSRC2 R/W 0 R/W 1 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 reserved RO 0 14 RO 0 13 PWRDN2 R/W 1 R/W 0 12 reserved SYSDIV2 R/W 0 11 BYPASS2 R/W 1 R/W 1 10 R/W 1 9 reserved Type Reset RO 0 RO 0 RO 0 Bit/Field 31 Name USERCC2 Type R/W Reset 0 Description Use RCC2 When set, overrides the RCC register fields. 30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-3 on page 167 for programming guidelines. 28:23 SYSDIV2 R/W 0x0F 22:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. September 04, 2010 Texas Instruments-Production Data 185 System Control Bit/Field 11 Name BYPASS2 Type R/W Reset 1 Description Bypass PLL When set, bypasses the PLL for the clock source. See Table 5-3 on page 167 for programming guidelines. 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Oscillator Source Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 0x4 0x5 0x6 0x7 Reserved Reserved Reserved 32 kHz 32. 768-kHz external oscillator 6:4 OSCSRC2 R/W 0x1 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 186 Texas Instruments-Production Data September 04, 2010 Stellaris® LM3S1110 Microcontroller Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F. E000 Offset 0x144 Type R/W, reset 0x0780. 0000 31 30 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 R/W 0 12 R/W 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 R/W 1 7 RO 0 6 RO 0 5 DSOSCSRC R/W 0 R/W 0 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 DSDIVORIDE R/W 1 10 R/W 1 9 Bit/Field 31:29 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]