User manual TEXAS INSTRUMENTS STELLARIS LM3S1439 DATA SHEET REV D

[. . . ] TE X AS I NS TRUM E NTS - P RO DUCTION D ATA Stellaris® LM3S1439 Microcontroller D ATA SH E E T D S -LM 3S 1439 - 7 3 9 3 C opyri ght © 2007-2010 Texas Instruments Incorporated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. [. . . ] With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1. 2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. 178 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1439 Microcontroller 9. 1. 6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9. 2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 179 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-2 on page 179 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 9-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Value AFSEL Digital Input (GPIO) Digital Output (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2C) Digital Input (Timer CCP) Digital Input (QEI) Digital Output (PWM) Digital Output (Timer PWM) Digital Input/Output (SSI) Digital Input/Output (UART) Analog Input (Comparator) Digital Output (Comparator) 0 0 0 1 1 1 1 1 1 1 0 1 DIR 0 1 1 X X X X X X X 0 X a ODR 0 0 1 1 0 0 0 0 0 0 0 0 DEN 1 1 1 1 1 1 1 1 1 1 0 1 PUR ?X=Ignored (don't care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-2. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger 0=edge 1=level Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIS X X X X X 0 X X June 23, 2010 Texas Instruments-Production Data 179 General-Purpose Input/Outputs (GPIOs) Table 9-2. GPIO Interrupt Configuration Example (continued) Register Desired Interrupt Event Trigger 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don't care bit) 0 0 0 0 0 1 0 0 X X X X X 1 X X Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIBE X X X X X 0 X X 9. 3 Register Map Table 9-3 on page 181 lists the GPIO registers. The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base address: GPIO Port A: 0x4000. 4000 GPIO Port B: 0x4000. 5000 GPIO Port C: 0x4000. 6000 GPIO Port D: 0x4000. 7000 GPIO Port E: 0x4002. 4000 GPIO Port F: 0x4002. 5000 GPIO Port G: 0x4002. 6000 GPIO Port H: 0x4002. 7000 Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000. 0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000. 0080 while the default reset value for Port C is 0x0000. 000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000. 00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. 180 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1439 Microcontroller Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000. 007F while the default reset value of GPIOCR for Port C is 0x0000. 00F0. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]