User manual TEXAS INSTRUMENTS STELLARIS LM3S1R21 DATA SHEET

[. . . ] TE X AS I NS TRUM E NTS - ADVANCE I NFO RMAT ION Stellaris® LM3S1R21 Microcontroller D ATA SHE E T D S -LM 3S 1R 21 - 6 7 9 0 C opyri ght © 2007-2010 Texas Instruments Incorporated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. [. . . ] Based on the range selected, the number of external clocks used between certain operations (for example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used, then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower frequency is given, incorrect operation occurs. See "External Peripheral Interface (EPI)" on page 778 for timing details for the SDRAM mode. 11. 4. 1. 1 External Signal Connections The Table 11-3 on page 355 table defines how EPI module signals should be connected to SDRAMs. The table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive when interfacing to SDRAM, see page 319. Any unused EPI controller signals can be used as GPIOs or another alternate function. 354 Texas Instruments-Advance Information February 09, 2010 Stellaris® LM3S1R21 Microcontroller Table 11-3. EPI SDRAM Signal Connections EPI Signal EPI0S0 EPI0S1 EPI0S2 EPI0S3 EPI0S4 EPI0S5 EPI0S6 EPI0S7 EPI0S8 EPI0S9 EPI0S10 EPI0S11 EPI0S12 EPI0S13 EPI0S14 EPI0S15 EPI0S16 EPI0S17 EPI0S18 EPI0S19 EPI0S20-EPI0S27 EPI0S28 EPI0S29 EPI0S30 EPI0S31 a. If 2 signals are listed, connect the EPI signal to both pins. Only for 256/512 megabit SDRAMs A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 b SDRAM Signal a D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DQML DQMH CASn RASn not used WEn CSn CKE CLK BA0 BA1 11. 4. 1. 2 Refresh Configuration The refresh count is based on the external clock speed and the number of rows per bank as well as the refresh period. The RFSH field represents how many external clock cycles remain before an AUTO-REFRESH is required. The normal formula is: RFSH = (tRefresh_us / number_rows) / ext_clock_period A refresh period is normally 64 ms, or 64000 s. The number of rows is normally 4096 or 8192. The ext_clock_period is a value expressed in sec and is derived by dividing 1000 by the clock speed expressed in MHz. A typical SDRAM is 4096 rows per bank if the system clock is running at 50 MHz with an EPIBAUD register value of 0: RFSH = (64000/4096) / 0. 02 = 15. 625 s / 0. 02 s = 781. 25 The default value in the RFSH field is 750 decimal or 0x2EE to allow for a margin of safety and providing 15 s per refresh. It is important to note that this number should always be smaller or equal to what is required by the above equation. For example, if running the external clock at 25 MHz (40 ns per clock period), 390 is the highest number that may be used. Note that the external February 09, 2010 Texas Instruments-Advance Information 355 External Peripheral Interface (EPI) clock may be 25 MHz when the system clock is 25 MHz or when the system clock is 50 MHz and configuring the COUNT0 field in the EPIBAUD register to 1 (divide by 2). If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost. 11. 4. 1. 3 Bus Interface Speed The EPI Controller SDRAM interface can operate up to 50 MHz. The COUNT0 field in the EPIBAUD register configures the speed of the EPI clock. For system clock (SysClk) speeds up to 50 MHz, the COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SysClk. However, if SysClk is running at higher speeds, the bus interface can run only as fast as half speed, and the COUNT0 field must be configured to at least 0x0001. 11. 4. 1. 4 Non-Blocking Read Cycle Figure 11-2 on page 356 shows a non-blocking read cycle of n halfwords; n can be any number greater than or equal to 1. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]