User manual TEXAS INSTRUMENTS TMS320C2810 DATA MANUAL REV R

[. . . ] TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS174R April 2001 ­ Revised May 2010 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 www. ti. com Contents 1 2 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Double update PWM mode can be achieved by using this condition for compare value reload. Copyright © 2001­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 61 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 www. ti. com 4. 2. 6 PWM Characteristics Characteristics of the PWMs are as follows: · 16-bit registers · Wide range of programmable deadband for the PWM output pairs · Change of the PWM carrier frequency for PWM frequency wobbling as needed · Change of the PWM pulse widths within and after each PWM period as needed · External-maskable power and drive-protection interrupts · Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms · Minimized CPU overhead using auto-reload of the compare and period registers · The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register. ­ PDPINTA pin status is reflected in bit 8 of COMCONA register. ­ PDPINTB pin status is reflected in bit 8 of COMCONB register. · EXTCON register bits provide options to individually trip control for each PWM pair of signals 4. 2. 7 Capture Unit The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits. Capture units include the following features: · One 16-bit capture control register, CAPCONx (R/W) · One 16-bit capture FIFO status register, CAPFIFOx · Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base · Three 16-bit 2-level-deep FIFO stacks, one for each capture unit · Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)--one input pin per capture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit. ] · User-specified transition (rising edge, falling edge, or both edges) detection · Three maskable interrupt flags, one for each capture unit · The capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture function. 4. 2. 8 Quadrature-Encoder Pulse (QEP) Circuit Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin. 4. 2. 9 External ADC Start-of-Conversion EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively. 62 Peripherals Copyright © 2001­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www. ti. com SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 4. 3 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: · 12-bit ADC core with built-in S/H · Analog input: 0. 0 V to 3. 0 V (voltages above 3. 0 V produce full-scale conversion results) · Fast conversion rate: 80 ns at 25-MHz ADC clock, 12. 5 MSPS · 16-channel, MUXed inputs · Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 16 input channels · Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i. e. , two cascaded 8-state sequencers) · Sixteen result registers (individually addressable) to store conversion values ­ The digital value of the input analog voltage is derived by: Digital Value = 0, Digital Value = 4096 ´ Input Analog Voltage - ADCLO 3 when input £ 0 V when 0 V < input < 3 V when input ³ 3 V Digital Value = 4095, · · · · · Multiple triggers as sources for the start-of-conversion (SOC) sequence ­ S/W ­ software immediate start ­ EVA ­ Event manager A (multiple event sources within EVA) ­ EVB ­ Event manager B (multiple event sources within EVB) Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions EVA and EVB triggers can operate independently in dual-sequencer mode Sample-and-hold (S/H) acquisition time window has separate prescale control The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]