User manual TEXAS INSTRUMENTS TMS320C28345 DATA MANUAL REV B

[. . . ] TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Delfino Microcontrollers Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS516B March 2009 ­ Revised July 2010 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com Contents 1 TMS320C2834x ( DelfinoTM) MCUs 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Table 4-2 and Table 4-3 show the complete ePWM register set per module. EXTSOC1A POLSEL 0 EXTSOC1A ePWM1SOCA ePWM1 ePWM1SOCB ePWM2SOCA ePWM2 ePWM2SOCB ePWM3SOCA ePWM3 ePWM3SOCB ePWM4SOCA ePWM4 0 ePWM4SOCB ePWM5SOCA ePWM5 ePWM5SOCB ePWM6SOCA ePWM6 ePWM6SOCB 1 ePWM7SOCA ePWM7 ePWM7SOCB ePWM8SOCA ePWM8 ePWM8SOCB ePWM9SOCA ePWM9 ePWM9SOCB 1 EXTSOC3B POLSEL 0 EXTSOC3B 1 EXTSOC3A POLSEL 0 EXTSOC3A 1 EXTSOC2B POLSEL 0 0 1 EXTSOC2A POLSEL EXTSOC1B 1 EXTSOC1B POLSEL Pulse Stretcher, 32 HSPCLK Cycles Wide and Then to Chip Pins EXTSOC2A EXTSOC2B Figure 4-4. Generation of SOC Pulses to the External ADC Module 66 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 Table 4-2. ePWM1-4 Control and Status Registers NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) ePWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 ePWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 ePWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 ePWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register Trip Zone Control Register Trip Zone Enable Interrupt Register Trip Zone Flag Register Trip Zone Clear Register Trip Zone Force Register Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) DESCRIPTION Registers that are EALLOW protected. Copyright © 2009­2010, Texas Instruments Incorporated Peripherals 67 Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com Table 4-3. ePWM5-9 Control and Status Registers NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) ePWM5 0x6900 0x6901 0x6902 0x6903 0x6904 0x6905 0x6907 0x6908 0x6909 0x690A 0x690B 0x690C 0x690D 0x690E 0x690F 0x6910 0x6911 0x6912 0x6914 0x6915 0x6916 0x6917 0x6918 0x6919 0x691A 0x691B 0x691C 0x691D 0x691E 0x6920 ePWM6 0x6940 0x6941 0x6942 0x6943 0x6944 0x6945 0x6947 0x6948 0x6949 0x694A 0x694B 0x694C 0x694D 0x694E 0x694F 0x6950 0x6951 0x6952 0x6954 0x6955 0x6956 0x6957 0x6958 0x6959 0x695A 0x695B 0x695C 0x695D 0x695E 0x6960 ePWM7 0x6980 0x6981 0x6982 0x6983 0x6984 0x6985 0x6987 0x6988 0x6989 0x698A 0x698B 0x698C 0x698D 0x698E 0x698F 0x6990 0x6991 0x6992 0x6994 0x6995 0x6996 0x6997 0x6998 0x6999 0x699A 0x699B 0x699C 0x699D 0x699E 0x69A0 ePWM8 0x69C0 0x69C1 0x69C2 0x69C3 0x69C4 0x69C5 0x69C7 0x69C8 0x69C9 0x69CA 0x69CB 0x69CC 0x69CD 0x69CE 0x69CF 0x69D0 0x69D1 0x69D2 0x69D4 0x69D5 0x69D6 0x69D7 0x69D8 0x69D9 0x69DA 0x69DB 0x69DC 0x69DD 0x69DE 0x69E0 ePWM9 0x6600 0x6601 0x6602 0x6603 0x6604 0x6605 0x6607 0x6608 0x6609 0x660A 0x660B 0x660C 0x660D 0x660E 0x660F 0x6610 0x6611 0x6612 0x6614 0x6615 0x6616 0x6617 0x6618 0x6619 0x661A 0x661B 0x661C 0x661D 0x661E 0x6620 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register Trip Zone Control Register Trip Zone Enable Interrupt Register Trip Zone Flag Register Trip Zone Clear Register Trip Zone Force Register Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) Registers that are EALLOW protected. 68 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 Time-base (TB) TBPRD shadow (16) TBPRD active (16) CTR=PRD TBCTL[PHSEN] Counter up/down (16 bit) TBCTR active (16) 16 8 Phase control CTR = PRD CTR = ZERO CTR = CMPA CTR = CMPB CTR_Dir Event trigger and interrupt (ET) EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxSYNCI CTR=ZERO CTR_Dir TBPHSHR (8) TBCTL[SWFSYNC] (software forced sync) CTR=ZERO CTR=CMPB Disabled Sync in/out select Mux EPWMxSYNCO TBCTL[SYNCOSEL] TBPHS active (24) Counter compare (CC) CTR=CMPA CMPAHR (8) 16 8 CMPA active (24) Action qualifier (AQ) HiRes PWM (HRPWM) EPWMA EPWMxAO CMPA shadow (24) CTR=CMPB 16 EPWMB CMPB active (16) CMPB shadow (16) CTR = ZERO Dead band (DB) PWM chopper (PC) Trip zone (TZ) EPWMxBO EPWMxTZINT TZ1 to TZ6 Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections Copyright © 2009­2010, Texas Instruments Incorporated Peripherals 69 Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com 4. 4 High-Resolution PWM (HRPWM) The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are: · Significantly extends the time resolution capabilities of conventionally derived digital PWM · Typically used when effective PWM resolution falls below ~ 9­10 bits. This occurs at PWM frequencies greater than ~500 kHz when using a CPU/System clock of 300 MHz or ~375 kHz when using a CPU/system clock of 200 MHz. · This capability can be utilized in both duty cycle and phase-shift control methods. · Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module. · HRPWM capabilities are offered only on the A signal path of an ePWM module (i. e. , on the EPWMxA output). EPWMxB output has conventional PWM capabilities. 70 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 4. 5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) The device contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module. CTRPHS (Phase Register - 32-bit) APWM Mode CTR_OVF Delta Mode CTR [0-31] PRD [0-31] CMP [0-31] SYNCIn SYNCOut SYNC TSCTR (Counter - 32-bit) OVF RST PWM Compare Logic 32 CTR [0-31] 32 PRD [0-31] CTR=PRD CTR=CMP 32 CAP1 (APRD Active) APRD Shadow 32 LD LD1 Polarity Select MODE SELECT eCAPx 32 CMP [0-31] 32 CAP2 (ACMP Active) LD LD2 Polarity Select Event Qualifier Event Prescale Polarity Select 32 ACMP Shadow 32 CAP3 (APRD Shadow) LD LD3 32 CAP4 (ACMP Shadow) LD LD4 Polarity Select 4 Capture Events CEVT[1:4] 4 to PIE Interrupt Trigger and Flag Control CTR_OVF CTR=PRD CTR=CMP Continuous/ One-Shot Capture Control Figure 4-6. eCAP Functional Block Diagram Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 71 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com The eCAP modules are clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low, indicating that the peripheral clock is off. eCAP Control and Status Registers NAME TSCTR CTRPHS CAP1 CAP2 CAP3 CAP4 Reserved ECCTL1 ECCTL2 ECEINT ECFLG ECCLR ECFRC Reserved eCAP1 0x6A00 0x6A02 0x6A04 0x6A06 0x6A08 0x6A0A 0x6A0C0x6A12 0x6A14 0x6A15 0x6A16 0x6A17 0x6A18 0x6A19 0x6A1A0x6A1F eCAP2 0x6A20 0x6A22 0x6A24 0x6A26 0x6A28 0x6A2A 0x6A2C0x6A32 0x6A34 0x6A35 0x6A36 0x6A37 0x6A38 0x6A39 0x6A3A0x6A3F eCAP3 0x6A40 0x6A42 0x6A44 0x6A46 0x6A48 0x6A4A 0x6A4C0x6A52 0x6A54 0x6A55 0x6A56 0x6A57 0x6A58 0x6A59 0x6A5A0x6A5F eCAP4 0x6A60 0x6A62 0x6A64 0x6A66 0x6A68 0x6A6A 0x6A6C0x6A72 0x6A74 0x6A75 0x6A76 0x6A77 0x6A78 0x6A79 0x6A7A0x6A7F eCAP5 0x6A80 0x6A82 0x6A84 0x6A86 0x6A88 0x6A8A 0x6A8C0x6A92 0x6A94 0x6A95 0x6A96 0x6A97 0x6A98 0x6A99 0x6A9A0x6A9F eCAP6 0x6AA0 0x6AA2 0x6AA4 0x6AA6 0x6AA8 0x6AAA 0x6AAC0x6AB2 0x6AB4 0x6AB5 0x6AB6 0x6AB7 0x6AB8 0x6AB9 0x6ABA0x6ABF SIZE (x16) 2 2 2 2 2 2 8 1 1 1 1 1 1 6 DESCRIPTION Time-Stamp Counter Counter Phase Offset Value Register Capture 1 Register Capture 2 Register Capture 3 Register Capture 4 Register Reserved Capture Control Register 1 Capture Control Register 2 Capture Interrupt Enable Register Capture Interrupt Flag Register Capture Interrupt Clear Register Capture Interrupt Force Register Reserved 72 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 4. 6 Enhanced QEP Modules (eQEP1/2 /3) The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution. Figure 4-7 shows the block diagram of the eQEP module. System Control Registers To CPU EQEPxENCLK QCPRD QCAPCTL 16 16 QCTMRLAT QCPRDLAT QUTMR QUPRD 32 QEPCTL QEPSTS QFLG UTIME UTOUT QWDOG WDTOUT PIE EQEPxINT 16 QPOSLAT QPOSSLAT QPOSILAT 32 QPOSCNT QPOSINIT QPOSMAX 32 QPOSCMP 16 QEINT QFRC QCLR QPOSCTL Enhanced QEP (eQEP) Peripheral Position Counter/ Control Unit (PCCU) QCLK QDIR QI QS Quadrature Decoder PHE (QDU) PCSOUT QDECCTL 16 EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxI EQEPxS QWDTMR QWDPRD 16 Quadrature Capture Unit (QCAP) QCTMR 16 Registers Used by Multiple Units Figure 4-7. eQEP Functional Block Diagram Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Data Bus SYSCLKOUT 73 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com Table 4-5 provides a summary of the eQEP registers. eQEP Control and Status Registers NAME QPOSCNT QPOSINIT QPOSMAX QPOSCMP QPOSILAT QPOSSLAT QPOSLAT QUTMR QUPRD QWDTMR QWDPRD QDECCTL QEPCTL QCAPCTL QPOSCTL QEINT QFLG QCLR QFRC QEPSTS QCTMR QCPRD QCTMRLAT QCPRDLAT Reserved eQEP1 ADDRESS 0x6B00 0x6B02 0x6B04 0x6B06 0x6B08 0x6B0A 0x6B0C 0x6B0E 0x6B10 0x6B12 0x6B13 0x6B14 0x6B15 0x6B16 0x6B17 0x6B18 0x6B19 0x6B1A 0x6B1B 0x6B1C 0x6B1D 0x6B1E 0x6B1F 0x6B20 0x6B21 - 0x6B3F eQEP2 ADDRESS 0x6B40 0x6B42 0x6B44 0x6B46 0x6B48 0x6B4A 0x6B4C 0x6B4E 0x6B50 0x6B52 0x6B53 0x6B54 0x6B55 0x6B56 0x6B57 0x6B58 0x6B59 0x6B5A 0x6B5B 0x6B5C 0x6B5D 0x6B5E 0x6B5F 0x6B60 0x6B61 - 0x6B7F eQEP3 ADDRESS 0x6B80 0x6B82 0x6B84 0x6B86 0x6B88 0x6B8A 0x6B8C 0x6B8E 0x6B90 0x6B92 0x6B93 0x6B94 0x6B95 0x6B96 0x6B97 0x6B98 0x6B99 0x6B9A 0x6B9B 0x6B9C 0x6B9D 0x6B9E 0x6B9F 0x6BA0 0x6BBA1 - 0x6BBF eQEPx SIZE(x16)/ #SHADOW 2/0 2/0 2/0 2/1 2/0 2/0 2/0 2/0 2/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 31/0 REGISTER DESCRIPTION eQEP Position Counter eQEP Initialization Position Count eQEP Maximum Position Count eQEP Position-compare eQEP Index Position Latch eQEP Strobe Position Latch eQEP Position Latch eQEP Unit Timer eQEP Unit Period Register eQEP Watchdog Timer eQEP Watchdog Period Register eQEP Decoder Control Register eQEP Control Register eQEP Capture Control Register eQEP Position-compare Control Register eQEP Interrupt Enable Register eQEP Interrupt Flag Register eQEP Interrupt Clear Register eQEP Interrupt Force Register eQEP Status Register eQEP Capture Timer eQEP Capture Period Register eQEP Capture Timer Latch eQEP Capture Period Latch 74 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 4. 7 External ADC Interface The external ADC interface operation is configured, controlled, and monitored by the External SoC Configuration Register (EXTSOCCFG) at address 0x702E. EXTSOC1A POLSEL 0 EXTSOC1A ePWM1SOCA ePWM1 ePWM1SOCB ePWM2SOCA ePWM2 ePWM2SOCB ePWM3SOCA ePWM3 ePWM3SOCB ePWM4SOCA ePWM4 0 ePWM4SOCB ePWM5SOCA ePWM5 ePWM5SOCB ePWM6SOCA ePWM6 ePWM6SOCB 1 ePWM7SOCA ePWM7 ePWM7SOCB ePWM8SOCA ePWM8 ePWM8SOCB ePWM9SOCA ePWM9 ePWM9SOCB 1 EXTSOC3B POLSEL 0 EXTSOC3B 1 EXTSOC3A POLSEL 0 EXTSOC3A 1 EXTSOC2B POLSEL 0 0 1 EXTSOC2A POLSEL EXTSOC1B 1 EXTSOC1B POLSEL Pulse Stretcher, 32 HSPCLK Cycles Wide and Then to Chip Pins EXTSOC2A EXTSOC2B Figure 4-8. External ADC Interface Registers NAME EXTSOCCFG Copyright © 2009­2010, Texas Instruments Incorporated DESCRIPTION External SoC Configuration Register ADDRESS 0x00 702E 75 Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com 4. 8 Multichannel Buffered Serial Port (McBSP) Module The McBSP module has the following features: · Compatible to McBSP in TMS320C54xTM/ TMS320C55xTM DSP devices · Full-duplex communication · Double-buffered data registers that allow a continuous data stream · Independent framing and clocking for receive and transmit · External shift clock generation or an internal programmable frequency shift clock · A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits · 8-bit data transfers with LSB or MSB first · Programmable polarity for both frame synchronization and data clocks · Highly programmable internal clock and frame generation · Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices · Works with SPI-compatible devices · The following application interfaces can be supported on the McBSP: ­ T1/E1 framers ­ IOM-2 compliant devices ­ AC97-compliant devices (the necessary multiphase frame synchronization capability is provided. ) ­ IIS-compliant devices ­ SPI · McBSP clock rate, CLKG = CLKSRG (1 + CLKGDV ) where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]