User manual TEXAS INSTRUMENTS TMS320C5505 DATASHEET 08-2010

[. . . ] TMS320C5505 www. ti. com SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 TMS320C5505 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5505 1 Fixed-Point Digital Signal Processor 1. 1 12 Features ­ Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses ­ Software-Compatible With C55x Devices ­ Industrial Temperature Devices Available 320K Bytes Zero-Wait State On-Chip RAM, Composed of: ­ 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit ­ 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: ­ 8-/16-Bit NAND Flash, 1- and 4-Bit ECC ­ 8-/16-Bit NOR Flash ­ Asynchronous Static RAM (SRAM) ­ 16-bit SDRAM/mSDRAM (1. 8-, 2. 5-, 2. 75-, and 3. 3-V) Direct Memory Access (DMA) Controller ­ Four DMA With 4 Channels Each (16-Channels Total) Three 32-Bit General-Purpose Timers ­ One Selectable as a Watchdog and/or GP Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces Universal Asynchronous Receiver/Transmitter (UART) Serial-Port Interface (SPI) With Four Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Four Inter-IC Sound (I2S BusTM) for Data Transport · HIGHLIGHTS: · High-Perf/Low-Power, C55xTM Fixed-Point DSP ­ 16. 67/13. 33/10/8. 33/6. 66-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-, 150-MHz Clock Rate · 320K Bytes On-Chip RAM · 16-/8-Bit External Memory Interface (EMIF) · Two MultiMedia Card/Secure Digital I/Fs · Serial-Port I/F (SPI) With Four Chip-Selects · Four Inter-IC Sound (I2S BusTM) · USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input · Four Core Isolated Power Supply Domains · Four I/O Isolated Power Supply Domains · One Integrated LDO · Industrial Temperature Devices Available · 1. 05-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 3-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 4-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · FEATURES: · High-Performance, Low-Power, TMS320C55xTM Fixed-Point Digital Signal Processor ­ 16. 67-, 13. 33-, 10-, 8. 33-, 6. 66-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-, 150-MHz Clock Rate ­ One/Two Instruction(s) Executed per Cycle ­ Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) · · · · · · · · · · · 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C5505 SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com · Device USB Port With Integrated 2. 0 High-Speed PHY that Supports: ­ USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply · Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB · Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO · One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA) · Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator · On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) · 1. 05-V Core (60 or 75 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 3-V Core (100, 120 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 4-V Core (150 MHz), 1. 8-V, 2. 5-V, 2. 75-V or 3. 3-V I/Os · Applications: ­ Wireless Audio Devices (e. g. , Headsets, Microphones, Speakerphones, etc. ) ­ Echo Cancellation Headphones ­ Portable Medical Devices ­ Voice Applications ­ Industrial Controls ­ Fingerprint Biometrics ­ Software Defined Radio · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Fixed-Point Digital Signal Processor Submit Documentation Feedback Product Folder Link(s): TMS320C5505 Copyright © 2010, Texas Instruments Incorporated TMS320C5505 www. ti. com SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 1. 2 Description The device is a member of TI's TMS320C5000TM fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. [. . . ] To completely disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground. The RTC oscillator generates a clock when a 32. 768-KHz crystal is connected to the RTC_XI and RTC_XO pins. The 32. 768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h ­ 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground. For more information on crystal specifications for the RTC oscillator and the USB oscillator, see Section 6. 4, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins. 4. 3. 1 Clock Configurations After Device Reset After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the system clock to 12. 288 MHz (multiply the 32. 768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. In this case, the CLKIN frequency is expected to be 11. 2896 MHz, 12. 0 MHz, or 12. 288 MHz. While the bootloader tries to boot from the USB , the clock generator will be programmed to output approximately 36 MHz. 4. 3. 1. 1 Device Clock Frequency After the boot process is complete, the user is allowed to re-program the system clock generator to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). The user must adhere to various clock requirements when programming the system clock generator. For more information, see Section 6. 5, Clock PLLs. Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The bootloader register modification feature must not modify the Timer0 registers. Copyright © 2010, Texas Instruments Incorporated Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5505 47 TMS320C5505 SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com 4. 3. 1. 2 Peripheral Clock State The clock and reset state of each of peripheral is controlled through a set of system registers. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control register (PRCR) are used to assert and de-assert peripheral reset signals. At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP boots via the bootloader code in ROM. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]