User manual TEXAS INSTRUMENTS TMS320C5515 DATASHEET 08-2010

[. . . ] TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1. 1 12 Features and Two Internal Data/Operand Write Buses ­ Software-Compatible With C55x Devices ­ Industrial Temperature Devices Available 320K Bytes Zero-Wait State On-Chip RAM, Composed of: ­ 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit ­ 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: ­ 8-/16-Bit NAND Flash, 1- and 4-Bit ECC ­ 8-/16-Bit NOR Flash ­ Asynchronous Static RAM (SRAM) ­ SDRAM/mSDRAM (1. 8-, 2. 5-, 2. 75-, and 3. 3-V) Direct Memory Access (DMA) Controller ­ Four DMA With 4 Channels Each (16-Channels Total) Three 32-Bit General-Purpose Timers ­ One Selectable as a Watchdog and/or GP Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces Universal Asynchronous Receiver/Transmitter (UART) Serial-Port Interface (SPI) With Four Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Four Inter-IC Sound (I2S BusTM) for Data Transport · HIGHLIGHTS: · High-Perf/Low-Power, C55xTM Fixed-Point DSP ­ 16. 67/13. 33/10/8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate · 320K Bytes On-Chip RAM · 16-/8-Bit External Memory Interface (EMIF) · Two MultiMedia Card/Secure Digital I/Fs · Serial-Port I/F (SPI) With Four Chip-Selects · Four Inter-IC Sound (I2S BusTM) · USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input · Four Core Isolated Power Supply Domains · Four I/O Isolated Power Supply Domains · Three Integrated LDOs · Industrial Temperature Devices Available · 1. 05-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 3-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · FEATURES: · High-Performance, Low-Power, TMS320C55xTM Fixed-Point Digital Signal Processor ­ 16. 67-, 13. 33-, 10-, 8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate ­ One/Two Instruction(s) Executed per Cycle ­ Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) ­ Three Internal Data/Operand Read Buses · · · · · · · · · · · 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C5515 SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com · Device USB Port With Integrated 2. 0 High-Speed PHY that Supports: ­ USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply · Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB · Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO · Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively · Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator · On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) · 1. 05-V Core (60 or 75 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 3-V Core (100, 120 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · Applications: ­ Wireless Audio Devices (e. g. , Headsets, Microphones, Speakerphones, etc. ) ­ Echo Cancellation Headphones ­ Portable Medical Devices ­ Voice Applications ­ Industrial Controls ­ Fingerprint Biometrics ­ Software Defined Radio · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Fixed-Point Digital Signal Processor Submit Documentation Feedback Product Folder Link(s): TMS320C5515 Copyright © 2010, Texas Instruments Incorporated TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 1. 2 Description The device is a member of TI's TMS320C5000TM fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. [. . . ] BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets powered down and the POWERGOOD signal is not generated properly. After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a faster wake-up time with the expense power consumption of the Bandgap reference. 0 = On-chip LDOs and Analog POR are enabled. 1 = On-chip LDOs and Analog POR are disabled (shutdown). 0 RTCCLKOUTEN Clockout output enable bit. 1 = Clock output enabled. 3 WU_DIR 2 BG_PD 1 LDO_PD 46 Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5515 Copyright © 2010, Texas Instruments Incorporated TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 15 Reserved 8 R-0 7 Reserved 2 R-0 1 DSP_LDO_V 0 USB_LDO_EN R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-2. LDO Control Register (LDOCNTL) [7004h] Table 4-3. LDOCNTL Register Bit Descriptions BIT 15:2 1 NAME RESERVED DSP_LDO_V DSP_LDO voltage select bit. USB_LDOO pin is placed in high-impedance (Hi-Z) state. Read-only, writes have no effect. 0 USB_LDO_EN Table 4-4. LDO Controls Matrix RTCPMGT Register (0x1930) BG_PD Bit 1 Don't Care 0 0 0 LDO_PD Bit Don't Care 1 0 0 0 LDOCNTL Register (0x7004) USB_LDO_EN Bit Don't Care Don't Care 0 0 1 DSP_LDO_EN (Pin D12) Don't Care Don't Care Low High Low ANA_LDO OFF OFF ON ON ON DSP_LDO OFF OFF ON OFF ON USB_LDO OFF OFF OFF OFF ON Copyright © 2010, Texas Instruments Incorporated Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5515 47 TMS320C5515 SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com 4. 3 Clock Considerations The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system clock generator. The system clock generator features a software-programmable PLL multiplier and several dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of the 32. 768-KHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the state of the CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot change dynamically after reset. In addition, the DSP requires a reference clock for USB applications. The USB reference clock is generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI and USB_MXO pins. The USB reference clock is not required if the USB peripheral is not being used. To completely disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]