User manual TEXAS INSTRUMENTS TMS320C6678 DATA MANUAL 11-2010

[. . . ] TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS691 November 2010 TMS320C6678 Data Manual SPRS691--November 2010 www. ti. com Release History Release 1. 0 Date November 2010 Chapter/Topic All Description/Comments Initial Release 2 Release History Copyright 2010 Texas Instruments Incorporated TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS691--November 2010 Contents 1 Features . . 15 2. 1 2. 2 2. 3 2. 4 2. 5 Device Characteristics . . 25 Boot Modes Supported and PLL Settings . [. . . ] · POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from POR) is put into the reset state. · CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. · The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD (core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1. · Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low. · The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t7. · DVDD18 (1. 8 V) supply is ramped up followed coincidentally by HHV (1. 8 V). · Filtered versions of 1. 8 V can ramp simultaneously with DVDD18. · RESETSTAT is driven low once the DVDD18 supply is available. · All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device. · DVDD15 (1. 5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18. t2a t2b t2c t3 t4a 102 TMS320C6678 Peripheral Information and Electrical Specifications Copyright 2010 Texas Instruments Incorporated TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS691--November 2010 POR-Controlled Power Sequencing -- Core Before IO (Part 2 of 2) System State · RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR controlled boot both RESETFULL and RESET must be high before POR is driven high. · POR must continue to remain low for at least 100 s after power has stabilized. End Power Stabilization Phase · Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33. 33 nsec, so a delay of an additional 16 s is required before a rising edge of POR. The clock must be active during the entire 16 s. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]