User manual TEXAS INSTRUMENTS TMS320DM355 DATA MANUAL REV G

[. . . ] TMS320DM355 www. ti. com SPRS463G ­ SEPTEMBER 2007 ­ REVISED JUNE 2010 TMS320DM355 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM355 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) 1. 1 123 Features ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 8K-Byte ROM ­ Little Endian MPEG4/JPEG Coprocessor ­ Fixed Function Coprocessor Supports: · MPEG4 SP Codec at HD (720p), D1, VGA, SIF · JPEG Codec up to 50M Pixels per Second Video Processing Subsystem ­ Front End Provides: · Hardware IPIPE for Real-Time Image Processing · Up to 14-bit CCD/CMOS Digital Interface · 16-/8-bit Generic YcBcR-4:2 Interface (BT. 601) · 10-/8-bit CCIR6565/BT655 Interface · Up to 75-MHz Pixel Clock · Histogram Module · Resize Engine ­ Resize Images From 1/16x to 8x ­ Separate Horizontal/Vertical Control ­ Two Simultaneous Output Paths ­ Back End Provides: · Hardware On-Screen Display (OSD) · Composite NTSC/PAL video encoder output · 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Supports digital HDTV (720p/1080i) output for connection to external encoder External Memory Interfaces (EMIFs) ­ DDR2 and mDDR SDRAM 16-bit wide EMIF · Highlights ­ High-Performance Digital Media System-on-Chip (DMSoC) ­ Up to 270-MHz ARM926EJ-STM Clock Rate ­ MPEG4/JPEG Coprocessor Supports · Up to 720p MPEG4 SP · Up to 50M Pixels per Second JPEG ­ Video Processing Subsystem · Hardware IPIPE for Real-Time Image Processing · Up to 14-bit CCD/CMOS Digital Interface · Histogram Module · Resize Image 1/16x to 8x · Hardware On-Screen Display · Supports digital HDTV (720p/1080i) output for connection to external encoder ­ Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2. 0, 3 UARTs and 3 SPIs ­ Configurable Power-Saving Modes ­ On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART ­ Extended Temperature 135- and 216-MHz Devices are Available ­ 3. 3-V and 1. 8-V I/O, 1. 3-V Core ­ Debug Interface Support ­ 337-Pin Ball Grid Array at 65 nm Process Technology · High-Performance Digital Media System-on-Chip (DMSoC) ­ 135-, 216-, and 270-MHz ARM926EJ-STM Clock Rate ­ Fully Software-Compatible With ARM9TM ­ Extended temperature support for 135- and 216-MHz devices · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC 1 · · · · 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. Copyright © 2007­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM355 SPRS463G ­ SEPTEMBER 2007 ­ REVISED JUNE 2010 www. ti. com · · · · · · · · · With 256 MByte Address Space (1. 8-V I/O) ­ Asynchronous16-/8-bit Wide EMIF (AEMIF) · Flash Memory Interfaces ­ NAND (8-/16-bit Wide Data) ­ OneNAND(16-bit Wide Data) Flash Card Interfaces ­ Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) ­ SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2. 0 High-Speed PHY that Supports ­ USB 2. 0 Full and High-Speed Device ­ USB 2. 0 Low, Full, and High-Speed Host Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) One 64-Bit Watch Dog Timer Three UARTs (One fast UART with RTS and CTS Flow Control) Three Serial Port Interfaces (SPI) each with two Chip-Selects One Master/Slave Inter-Integrated Circuit (I2C) Bus® Two Audio Serial Port (ASP) ­ I2S and TDM I2S ­ AC97 Audio Codec Interface · · · · · · · · · · · · ­ S/PDIF via Software ­ Standard Voice Codec Interface (AIC12) ­ SPI Protocol (Master Mode Only) Four Pulse Width Modulator (PWM) Outputs Four RTO (Real Time Out) Outputs Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash (with SPI EEPROM Boot option), MMC/SD, or UART Configurable Power-Saving Modes Crystal or External Clock Input (typically 24 MHz or 36 MHz) Flexible PLL Clock Generators Debug Interface Support ­ IEEE-1149. 1 (JTAG) Boundary-Scan-Compatible ­ ETBTM (Embedded Trace BufferTM) with 4K-Bytes Trace Buffer memory ­ Device Revision ID Readable by ARM 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0. 65-mm Ball Pitch 90nm Process Technology 3. 3-V and 1. 8-V I/O, 1. 3-V Internal Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) Copyright © 2007­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM355 TMS320DM355 www. ti. com SPRS463G ­ SEPTEMBER 2007 ­ REVISED JUNE 2010 1. 2 Description The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. [. . . ] The PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1 (typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3. 5 and Section 3. 6. The default state of the PLLs is reflected in the default state of the register bits in the PLLC registers. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3) for PLLC register descriptions. 3. 11. 3 Power Domain and Module State Configuration Only a subset of modules are enabled after reset by default. Table 3-22 shows which modules are enabled after reset. Table 3-22 as shows that the following modules are enabled depending on the sampled state of the device configuration pins: EDMA (CC, TC0 and TC1), AEMIF, MMC/SD0, UART0, and Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] = 11 - Enable UART) select UART boot mode. For more information on module configuration refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3). 86 Detailed Device Description Submit Documentation Feedback Product Folder Link(s): TMS320DM355 Copyright © 2007­2010, Texas Instruments Incorporated TMS320DM355 www. ti. com SPRS463G ­ SEPTEMBER 2007 ­ REVISED JUNE 2010 Table 3-22. Module Configuration Default States Module Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Module Name VPSS Master VPSS Slave EDMA (CC) EDMA (TC0) EDMA (TC1) Timer3 SPI1 MMC/SD1 ASP1 USB PWM3 SPI2 RTO DDR EMIF AEMIF Power Domain AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn Power Domain State ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Module State SyncRst SyncRst BTSEL[1:0] = 00 ­ Enable (NAND, SPI) BTSEL[1:0] = 01 ­ Enable (OneNAND) BTSEL[1:0] = 10 ­ SyncRst (MMC/SD) BTSEL[1:0] = 11 ­ Enable (UART) SyncRst SyncRst SyncRst SyncRst SyncRst SyncRst SyncRst SyncRst SyncRst BTSEL[1:0] = 00 ­ Enable (NAND, SPI) BTSEL[1:0] = 01 ­ Enable (OneNAND) BTSEL[1:0] = 10 ­ SyncRst (MMC/SD) BTSEL[1:0] = 11 ­ Enable (UART) 15 MMC/SD0 AlwaysOn ON BTSEL[1:0] = 00 ­ SyncRst (NAND, SPI) BTSEL[1:0] = 01 ­ SyncRst (OneNAND) BTSEL[1:0] = 10 ­ Enable (MMC/SD) BTSEL[1:0] = 11 ­ SyncRst (UART) 16 17 18 19 Reserved ASP I2C UART0 Reserved AlwaysOn AlwaysOn AlwaysOn Reserved ON ON ON Reserved SyncRst SyncRst BTSEL[1:0] = 00 ­ SyncRst (NAND, SPI) BTSEL[1:0] = 01 ­ SyncRst (OneNAND) BTSEL[1:0] = 10 ­ SyncRst (MMC/SD) BTSEL[1:0] = 11 ­ Enable (UART) 20 21 22 UART1 UART2 SPI0 AlwaysOn AlwaysOn AlwaysOn ON ON ON SyncRst SyncRst BTSEL[1:0] = 00 ­ Enable (NAND, SPI) BTSEL[1:0] = 01 ­ SyncRst (OneNAND) BTSEL[1:0] = 10 ­ Enable (MMC/SD) BTSEL[1:0] = 11 ­ Enable (UART) 23 24 25 26 27 PWM0 PWM1 PWM2 GPIO TIMER0 AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn ON ON ON ON ON SyncRst SyncRst SyncRst SyncRst BTSEL[1:0] = 00 ­ Enable (NAND, SPI) BTSEL[1:0] = 01 ­ Enable (OneNAND) BTSEL[1:0] = 10 ­ Enable (MMC/SD) BTSEL[1:0] = 11 ­ Enable (UART) 28 TIMER1 AlwaysOn ON SyncRst Detailed Device Description Submit Documentation Feedback Product Folder Link(s): TMS320DM355 87 Copyright © 2007­2010, Texas Instruments Incorporated TMS320DM355 SPRS463G ­ SEPTEMBER 2007 ­ REVISED JUNE 2010 www. ti. com Table 3-22. Module Configuration (continued) Default States 29 30 31 32 33 34 35 36 37 38 39 40 TIMER2 System Module ARM BUS BUS BUS BUS BUS BUS BUS Reserved VPSS DAC AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn Reserved Always On ON ON ON ON ON ON ON ON ON ON Reserved ON Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Reserved SyncRst 3. 11. 4 ARM Boot Mode Configuration The input pins BTSEL[1:0] determine whether the ARM will boot from its ROM or from the Asynchronous EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] = 00, 10, or 11), a jump to the start of internal ROM (address 0x0000: 8000) is forced into the first fetched instruction word. The embedded ROM boot loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine the desired boot method, and branches to the appropriate boot routine (i. e. , a NAND/SPI, MMC/SD, or UART loader routine). If AEMIF boot is selected (BTSEL[1:0] = 01), a jump to the start of AEMIF (address 0x0200: 0000) is forced into the first fetched instruction word. The ARM then continues executing from external asynchronous memory using the default AEMIF timings until modified by software. NOTE For AEMIF boot, the OneNAND must be connected to the first AEMIF chip select space (EM_CE0). Also, the AEMIF does not support direct execution from NAND Flash. Boot modes are further described in Section 3. 12. 3. 11. 5 AEMIF Configuration 3. 11. 5. 1 AEMIF Pin Configuration The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0] to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in Section 3. 9. Also, see the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide (literature number SPRUED1) for more information on the AEMIF. 3. 11. 5. 2 AEMIF Timing Configuration When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is 88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz clock at MXI1, the AEMIF is configured to run at 6 MHz/88 which equals approximately 68 kHz by default. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]