User manual TEXAS INSTRUMENTS TMS320DM640 DATA MANUAL 10-2010

[. . . ] TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS222F June 2003 - Revised October 2010 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. This page intentionally left blank Revision History Revision History This data sheet revision history highlights the technical changes made to the SPRS222E device-specific data sheet to make it an SPRS222F revision. PAGE(s) NO. 82 Added note for VOH and VOL. ADDS/CHANGES/DELETES June 2003 - Revised October 2010 SPRS222F 3 Contents Contents Section 1 Page 15 15 16 18 20 20 22 25 28 30 31 32 32 36 42 64 64 65 65 66 67 68 68 68 69 69 69 72 74 76 77 77 82 82 82 83 84 84 84 84 84 Device Overview . [. . . ] Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. § Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz EMIF for -500 and -400 speeds). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows: High-DSP-Activity Model: CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions; L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate Low-DSP-Activity Model: CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power Consumption Summary application report (literature number SPRA962). ¶ Single pin driving I OH / IOL = MAX. 82 SPRS222F June 2003 - Revised October 2010 DM641/DM640 Peripheral Information and Electrical Specifications 4 4. 1 4. 1. 1 DM641/DM640 Peripheral Information and Electrical Specifications Parameter Information Parameter Information Device-Specific Information Tester Pin Electronics Data Sheet Timing Reference Point 42 3. 5 nH Transmission Line Z0 = 50 (see note) Output Under Test Device Pin (see note) 4. 0 pF 1. 85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 4-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 4. 1. 1. 1 Signal Transition Levels All input and output timing parameters are referenced to 1. 5 V for both "0" and "1" logic levels. Vref = 1. 5 V Figure 4-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels 4. 1. 1. 2 Signal Transition Rates All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns). June 2003 - Revised October 2010 SPRS222F 83 Parameter Information 4. 1. 1. 3 AC Transient Rise/Fall Time Specifications Figure 4-4 and Figure 4-5 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet. t = 0. 3 tc (max) VOS (max) Minimum Risetime Waveform Valid Region Ground VIH (min) Figure 4-4. AC Transient Specification Rise Time tc = the peripheral cycle time in nanoseconds (ns). t = 0. 3 tc(max) VIL (max) VUS (max) Ground Figure 4-5. AC Transient Specification Fall Time tc = the peripheral cycle time in nanoseconds (ns). 4. 1. 1. 4 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]