User manual TEXAS INSTRUMENTS TMS320DM6441 DATASHEET 08-2010

[. . . ] TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 TMS320DM6441 Digital Media System-on-Chip Check for Samples: TMS320DM6441 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ Embedded ICE-RTTM Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM · Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug · Endianness: Little Endian for ARM and DSP · Video Imaging Co-Processor (VICP) · Video Processing Subsystem ­ Front End Provides: · CCD and CMOS Imager Interface · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Preview Engine for Real-Time Image Processing · Glueless Interface to Common Video Decoders · Histogram Module · Auto-Exposure, Auto-White Balance, and Auto-Focus Module · Resize Engine ­ Resize Images From 1/4x to 4x ­ Separate Horizontal/Vertical Control · High-Performance Digital Media SoC ­ C64x+TM DSP Clock Rate · 405-MHz (Max) at 1. 05 V or 513-MHz (Max) at 1. 2 V ­ ARM926EJ-STM Clock Rate · 202. 5-MHz (Max) at 1. 05 V or 256-MHz (Max) at 1. 2 V ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2006­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6441 SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 www. ti. com · Video Processing Subsystem (Continued) ­ Back End Provides: · Hardware On-Screen Display (OSD) · Four 54-MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to Two Video Windows · External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ CompactFlash Controller With True IDE Mode ­ SmartMedia ­ Memory Stick® and Memory Stick PROTM · Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three UARTs (One with RTS and CTS Flow Control) · One Serial Port Interface (SPI) With Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Audio Serial Port (ASP) ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) · 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) · VLYNQTM Interface (FPGA Interface) · Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host · Three Pulse Width Modulator (PWM) Outputs · On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART · ATA/ATAPI I/F (ATA/ATAPI-5 Specification) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch · 0. 09-µm/6-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 05-V or 1. 2-V internal · Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging ­ Portable Media Players 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 Copyright © 2006­2010, Texas Instruments Incorporated TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 1. 2 Description The TMS320DM6441 (also referenced as DM6441) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] Enable EMIFA EM_CS5 function on GPIO[8] Enable EMIFA EM_CS4 function on GPIO[9] Reserved EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. Description Enable EMAC and MDIO function on default GPIO3V[0:16] pins. 76 Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 Copyright © 2006­2010, Texas Instruments Incorporated TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 3. 5. 5 PINMUX1 Register Description The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing fields are given in Section 3. 5. 6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. PINMUX1 Register 31 RESERVED R-0000 0000 0000 0 15 RESERVED R-0000 0 11 10 ASP R/W-0 9 MSKT R/W-0 8 SPI R/W-0 7 I2C R/W-0 6 R/W-0 5 R/W-0 4 R/W-0 3 19 18 TIMIN R/W-0 2 UART2 R/W-0 17 CLK1 R/W-0 1 UART1 R/W-0 16 CLK0 R/W-0 0 UART0 R/W-0 PWM2 PWM1 PWM0 U2FLO R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-15. PINMUX1 Register Field Descriptions Bit 31 - 19 18 17 16 15 - 11 10 9 8 7 6 5 4 3 2 1 0 Field RESERVED TIMIN CLK1 CLK0 RESERVED ASP MSKT SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0 Value Reserved Enable TIM_IN function on default GPIO[49] pin Enable CLK_OUT1 function on default GPIO[49] pin Enable CLK_OUT0 function on default GPIO[48] pin Reserved Enable ASP function on default GPIO[29:34] pins Enable Memory Stick/Memory Stick PRO function on default MMC/SD/SDIO pins Enable SPI function on default GPIO[37, 39:42] pins Enable I2C function on default GPIO[43:44] pins Enable PWM2 function on default GPIO[47] pin Enable PWM1 function on default GPIO[46] pin Enable PWM0 function on default GPIO[45] pin Enable UART2 flow control function on default VPFE CI[5:4]/CCD_DATA[13:12] pins Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14] pins Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins Enable UART0 function on default GPIO[35:36] pins Description Copyright © 2006­2010, Texas Instruments Incorporated Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 77 TMS320DM6441 SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 www. ti. com 3. 5. 6 Pin Multiplexing Register Field Details The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are described in the following sections. 3. 5. 6. 1 EMAC and GPIO3V Pin Multiplexing The EMAC pin functions are selected as shown in Table 3-16. The functionality for each of the individual pins affected by the PINMUX0 field settings is given in Table 3-17. EMAC and GPIO3V Pin Multiplexing Control EMACEN 0 1 GPIO3V EMAC PIN FUNCTIONALITY SELECTED Table 3-17. EMAC and GPIO3V Multiplexed Pins GPIO GPIO3V[0] GPIO3V[1] GPIO3V[2] GPIO3V[3] GPIO3V[4] GPIO3V[5] GPIO3V[6] GPIO3V[7] GPIO3V[8] GPIO3V[9] GPIO3V[10] GPIO3V[11] GPIO3V[12] GPIO3V[13] GPIO3V[14] GPIO3V[15] GPIO3V[16] TXEN TXCLK COL TXD[0] TXD[1] TXD[2] TXD[3] RXD[0] RXD[1] RXD[2] RXD[3] RXCLK RXDV RXER CRS MDIO MDCLK EMAC 78 Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 Copyright © 2006­2010, Texas Instruments Incorporated TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 3. 5. 6. 2 VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing The CCD and LCD controllers in the VPSS require multiplex control bit settings for certain modes of operation. Bits within the PinMux0 register, which select between the CCD or LCD control signal function and GPIO, are summarized in Table 3-18. VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing PINMUX0 REGISTER FIELDS CFLDEN 0 1 (1) LFLDEN 0 1 CWE 0 1 LOEEN 0 1 C_FIELD/ R0/ GPIO[4] R0/GPIO[4] (1) C_FIELD MULTIPLEXED PINS LCD_FIELD/ B0/ GPIO[3] B0/GPIO[3] (1) LCD_FIELD C_WE/ GPIO[1] GPIO[1] C_WE LCD_OE/ GPIO[0] GPIO[0] LCD_OE - Depends on RGB888 bit setting, see Table 3-19. 3. 5. 6. 3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19 and Table 3-20. Enabling PWM2, PWM1, CCD, and LCD functionality overrides the RGB modes. RGB666 interface pin functionality requires setting the RGB666 PINMUX0 register bit field to `1' and PINMUX1 register bit fields PWM2 and PWM1 to `0'. Proper RGB888 interface operation requires setting PINMUX0 register bit field RGB888 to `1' and bit fields PWM2, PWM1, CFLDEN, and LFLDEN must be set to `0'. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS RGB888 0 0 1 RGB666 0 1 PWM2 0 1 0 0 PWM1 0 1 0 0 CFLDEN 0 1 0 0 PWM2/ LFLDEN B2/ GPIO[47] 0 1 0 0 GPIO[47] PWM2 B2 B2 MULTIPLEXED PINS PWM1/ R2/ GPIO[46] GPIO[46] PWM1 R2 R2 C_FIELD/ R0/ GPIO[4] GPIO[4] C_FIELD GPIO[4] R0 LCD_FIELD/ B0/ GPIO[3] GPIO[3] LCD_FIELD GPIO[3] B0 Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS RGB888 0 1 PWM2 0 0 PWM1 0 0 CFLDEN 0 0 LFLDEN 0 0 R1/ GPIO[38] GPIO[38] R1 MULTIPLEXED PINS B1/ GPIO[6] GPIO[6] B1 G1/ GPIO[5] GPIO[5] G1 G0/ GPIO[2] GPIO[2] G0 Copyright © 2006­2010, Texas Instruments Incorporated Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 79 TMS320DM6441 SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 www. ti. com 3. 5. 6. 4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1 if the buffer is not being used (i. e. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]