User manual TEXAS INSTRUMENTS TMS320DM6443 DATASHEET 08-2010

[. . . ] TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 TMS320DM6443 Digital Media System-on-Chip Check for Samples: TMS320DM6443 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM · Emulation Trace BufferTM (ETB11TM) With 4-KB Memory for ARM9 Debug · Endianness: Little Endian for ARM and DSP · Video Processing Subsystem ­ Resize Engine Provides: · Resize Images From 1/4x to 4x · Separate Horizontal and Vertical Control ­ Back End Provides: · Hardware On-Screen Display (OSD) · 4 - 54 MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-Bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to 2 Video Windows · High-Performance Digital Media SoC ­ 594-MHz C64x+TM Clock Rate ­ 297-MHz ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2005­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6443 SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 www. ti. com · External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ Compact Flash Controller With True IDE Mode ­ SmartMedia · Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three UARTs (One with RTS and CTS Flow Control) · One Serial Peripheral Interface (SPI) with Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Audio Serial Port (ASP) ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) · 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) · VLYNQTM Interface (FPGA Interface) · Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed (480 Mbps) Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) · Three Pulse Width Modulator (PWM) Outputs · On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART · ATA/ATAPI I/F (ATA/ATAPI-6 Specification) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/6-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 2-V Internal · Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 1. 2 Description The TMS320DM6443 (also referenced as DM6443) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] DM6443 Multiplexed Peripheral Pins and Multiplexing Controls MULTIPLEXED PERIPHERALS PRIMARY (DEFAULT) FUNCTION SECONDARY (1) FUNCTION TERTIARY (2) FUNCTION SECONDARY REGISTER/PIN (3) CONTROL PinMux0:HPIEN, Pins:BTSEL[1:0] = 10 TERTIARY REGISTER/PIN (3) CONTROL EMIFA (NAND), HPI EMIFA (NAND): HPI: EM_A[1] (ALE), HHWIL, HCNTL0, EM_A[2] (CLE), HCS EM_CS2, EM_CS3 EMIFA, HPI, ATA (CF) EMIFA (NAND), HPI, ATA (CF) EMIFA: EM_D[0:15], EM_BA[0] EMIFA (NAND): R/W, EM_WAIT (RDY/BSY), EM_OE (RE), EM_WE (WE) GPIO:GPIO[0] GPIO:GPIO[2] ATA (CF): DD[0:15], DA0 ATA (CF): INTRQ, IORDY, DIOR(IORD) , DIOW (IOWR) VPBE: LCD_OE VPBE: RGB888 G0 VPBE: RGB888 B0 VPBE: RGB888 R0 VPBE: RGB888 G1, B1, R1 EMIFA: EM_CS5 EMIFA: EM_CS4 EMIFA: EM_A[21:14] EMIFA: EM_A[13:3] VLYNQ: VLYNQ_CLOCK VLYNQ: VLYNQ_SCRUN VLYNQ: VLYNQ_TXD[0:3], VLYNQ_RXD[0:3] VPBE: LCD_FIELD HPI: HD[0:15], HINT HPI: HR/W, HRDY, HDS1, HDS2 PinMux0:ATAEN PinMux0:HPIEN, Pins:BTSEL[1:0] = 10 PinMux0:HPIEN, Pins:BTSEL[1:0] = 10 PinMux0:ATAEN VPBE LCD, GPIO VPBE RGB888, GPIO PinMux0:LOEEN PinMux0:RGB888 PinMux0:RGB888 PinMux0:RGB888 PinMux0:RGB888 PinMux0:LFLDEN VPBE GPIO:GPIO[3] LCD/RGB888, GPIO VPBE RGB888, GPIO VPBE RGB888, GPIO EMIFA, VLYNQ, GPIO EMIFA, VLYNQ, GPIO EMIFA, VLYNQ, GPIO EMIFA, GPIO GPIO:GPIO[4] GPIO: GPIO[5:6, 38] GPIO:GPIO[8] GPIO:GPIO[9] GPIO: GPIO[10:17] GPIO: GPIO[18:28] PinMux0:AECS5 PinMux0:AECS4 PinMux0:AEAW, Pins:DAEAW[4:0] PinMux0:AEAW, Pins:DAEAW[4:0] PinMux0:VLYNQEN PinMux0:VLSCREN PinMux0:VLYNQEN, PinMux0:VLYNQWD[1:0] (1) (2) (3) 72 When the Secondary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO) and Tertiary functions are disabled. When the Tertiary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO), Secondary, and other Tertiary functions are disabled. Pin states are sampled at power on reset and written into the register fields. Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 Table 3-13. DM6443 Multiplexed Peripheral Pins and Multiplexing Controls (continued) MULTIPLEXED PERIPHERALS ASP, GPIO UART0, GPIO SPI, GPIO PRIMARY (DEFAULT) FUNCTION GPIO: GPIO[29:34] GPIO: GPIO[35:36] GPIO: GPIO[37, 39:41] SECONDARY (1) FUNCTION ASP: (all pins) (4) UART0: RXD, TXD SPI: SPI_EN0, SPI_CLK, SPI_DI, SPI_DO SPI: SPI_EN1 I2C: SCL, SDA PWM0 VPBE: PWM1: RGB666/RGB888 PWM1 R2 VPBE: PWM2: RGB666/RGB888 PWM2 B2 CLK_OUT0 CLK_OUT1 ATA: ATA_CS0, ATA_CS1 EMIFA: EM_BA[1] EMIFA: EM_A[0] EMAC: (all pins, except CRS) (5) EMAC: CRS, MDIO: MDIO, MDCLK ATA (CF): UART1: TXD, RXD DMACK, DMARQ UART2: UART_RXD2, UART_TXD2 UART2: UART_CTS2, UART_RTS2 ATA (CF): DA1 ATA (CF): DA2/ HPI: HCNTL1 TIMER0: TIM_IN ATA: HDDIR TERTIARY (2) FUNCTION SECONDARY REGISTER/PIN (3) CONTROL PinMux1:ASP PinMux1:UART0 PinMux1:SPI TERTIARY REGISTER/PIN (3) CONTROL SPI, ATA, GPIO I2C, GPIO PWM0, GPIO PWM1, VPBE (RGB666/RGB888), GPIO PWM2, VPBE (RGB666/RGB888), GPIO ClockOut0, GPIO GPIO:GPIO[42] GPIO: GPIO[43:44] GPIO:GPIO[45] GPIO:GPIO[46] PinMux1:SPI PinMux1:I2C PinMux1:PWM0 PinMux0:RGB666/ PinMux0:RGB888 PinMux0:RGB666/ PinMux0:RGB888 PinMux1:CLK0 PinMux1:CLK1 PinMux0:ATAEN PinMux0:HDIREN PinMux1:PWM1 GPIO:GPIO[47] PinMux1:PWM2 GPIO:GPIO[48] ClockOut1, TIMER0, GPIO:GPIO[49] GPIO ATA, GPIO GPIO: GPIO[50:51] GPIO:GPIO[52] GPIO:GPIO[53] PinMux1:TIM_IN EMIFA, GPIO, ATA (CF) EMIFA, HPI, ATA (CF), GPIO EMAC, GPIO3V PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:EMACEN PinMux0:ATAEN PinMux0:ATAEN, PinMux0:HPIEN, Pins:BTSEL[1:0] = 10 GPIO: GPIO3V[0:13] GPIO: GPIO3V[14:16] EMAC, MDIO, GPIO3V PinMux0:EMACEN UART1, ATA (CF) UART2 N/A N/A PinMux0:ATAEN PinMux1:UART2 PinMux1:UART1 UART2 N/A PinMux1:UART2, PinMux1:U2FLO (4) (5) See Section 2. 7, Terminal Functions, for pin details. See Section 2. 7, Terminal Functions, for pin details. Copyright © 2005­2010, Texas Instruments Incorporated Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 73 TMS320DM6443 SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 www. ti. com 3. 5. 3 Peripheral Selection After Device Reset After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing of shared device pins between peripherals, as given in Section 2. 7, Terminal Functions. Section 3. 5. 4 (PINMUX0 Register Description), Section 3. 5. 5 (PINMUX1 Register Description), and Section 3. 5. 6 (Pin Multiplexing Register Field Details) identify the register settings necessary to configure specific multiplexed functions and show the primary (default) function after reset. 3. 5. 4 PINMUX0 Register Description The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins among EMAC, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on the PINMUX0 pin muxing fields are given in Section 3. 5. 6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. PINMUX0 Register (1) 31 EMACEN R/W-0 15 R/W-0 (1) 30 Rsvd R/W-0 14 R/W-0 29 HPIEN R/W-D 13 28 26 Reserved R/W-000 25 LFLDEN R/W-0 10 AECS4 R/W-0 24 LOEEN R/W-0 9 23 RGB888 R/W-0 22 RGB666 R/W-0 21 Reserved R-0000 5 4 18 17 ATAEN R/W-0 16 HDIREN R/W-0 0 12 11 AECS5 R/W-0 VLYNQEN VLSCREN VLYNQWD R/W-00 Reserved R-00000 AEAW R/W-LLLLL LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset For proper DM6443 device operation, always write a value of '0' to RSV bits 30, 27, and 26. Table 3-14. PINMUX0 Register Description Name EMACEN HPIEN LFLDEN LOEEN RGB888 RGB666 ATAEN HDIREN VLYNQEN VLSCREN VLYNQWD AECS5 AECS4 AEAW Description Enable EMAC and MDIO function on default GPIO3V[0:16] pins. Default value is derived from BTSEL[1:0] configuration inputs. HPIEN is 1 when the BTSEL[1:0] = 10 and HPIEN is 0 (the default state) when BTSEL[1:0] is 00, 01, or 11. Enable LCD_FIELD function on default GPIO[3] pin Enable LCD_OE function on default GPIO[0] pin Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins Enable VPBE RGB666 function on default GPIO[46:47] pins Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins Enable HDDIR function on default GPIO[42] pin Enable VLYNQ function on default GPIO[9, 10:17] pins Enable VLYNQ SCRUN function on default GPIO[9] pin VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3] functions on default GPIO[10:17] pins. Enable EMIFA EM_CS5 function on GPIO[8] Enable EMIFA EM_CS4 function on GPIO[9] EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. 74 Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 3. 5. 5 PINMUX1 Register Description The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing fields are given in Section 3. 5. 6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]