User manual TEXAS INSTRUMENTS TMS320DM6467T DATA MANUAL REV B

[. . . ] TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 TMS320DM6467T Digital Media System-on-Chip Check for Samples: TMS320DM6467T 1 Digital Media System-on-Chip (DMSoC) 1. 1 1 Features ­ 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 8K-Byte ROM Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines ­ Supports a Range of Encode, Decode, and Transcode Operations · H. 264, MPEG2, VC1, MPEG4 SP/ASP 150-MHz Video Port Interface (VPIF) ­ Two 8-Bit SD (BT. 656), Single 16-Bit HD (BT. 1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels ­ Two 8-Bit SD (BT. 656) or Single 16-Bit HD (BT. 1120) Video Display Channels Video Data Conversion Engine (VDCE) ­ Horizontal and Vertical Downscaling ­ Chroma Conversion (4:2:24:2:0) Two Transport Stream Interface (TSIF) Modules (One Parallel/Serial and One Serial Only) ­ TSIF for MPEG Transport Stream ­ Simultaneous Synchronous or Asynchronous Input/Output Streams ­ Absolute Time Stamp Detection ­ PID Filter With 7 PID Filter Tables ­ Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery · High-Performance Digital Media SoC ­ 1-GHz C64x+TM Clock Rate ­ 500-MHz ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 8000 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM ­ Industrial Temperature Devices Available · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 32K-Byte L1D Data RAM/Cache (2-Way Set-Associative) 1 · · · · · · · · Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009­2010, Texas Instruments Incorporated TMS320DM6467T SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 www. ti. com · External Memory Interfaces (EMIFs) ­ Up to 400-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) ­ Programmable Default Burst Size · 10/100/1000 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant (3. 3-V I/O Only) ­ Supports MII and GMII Media Independent Interfaces ­ Management Data I/O (MDIO) Module · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) · 32-Bit, 66-MHz, 3. 3 V Peripheral Component Interconnect (PCI) Master/Slave Interface ­ Conforms to PCI Specification 2. 3 · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) ­ Supports up to 1. 8432 Mbps UART ­ SIR and MIR (0. 576 MBAUD) ­ CIR With Programmable Data Encoding · One Serial Peripheral Interface (SPI) With Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Two Multichannel Audio Serial Ports (McASPs) ­ One Four Serializer Transmit/Receive Port ­ One Single DIT Transmit Port for S/PDIF · 32-Bit Host Port Interface (HPI) · VLYNQTM Interface (FPGA Interface) · Two Pulse Width Modulator (PWM) Outputs · ATA/ATAPI I/F (ATA/ATAPI-6 Specification) · Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · On-Chip ARM ROM Bootloader (RBL) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · 529-Pin Pb-Free BGA Package (ZUT Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/7-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 3-V Internal · Applications: ­ Video Encode/Decode/Transcode/Transrate ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging ­ Video Infrastructure ­ Video Conferencing · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Digital Media System-on-Chip (DMSoC) Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 1. 2 Description The TMS320DM6467T (also referenced as DM6467T) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. [. . . ] 01 = TS1 input selection enabled (muxed on UART0 pins). 10 = TS1 input selection enabled (muxed on VP_DOUT pins). 11 = TS1 input selection enabled (muxed on VP_DIN pins). TSIF0 Parallel/Serial Output Pin Mux Control (see Section 4. 7. 3. 4, TSIF0 Output Signal Muxing). 10 = TS0 parallel output muxing enabled (muxed with VP_DIN pins). 11 = TS0 serial output muxing enabled (muxed TS0_DOUT7 with UTXD1). TSIF0 Parallel/Serial Input Pin Mux Control (see Section 4. 7. 3. 3, TSIF0 Input Signal Muxing). 10 = TS0 parallel input muxing enabled (muxed with VP_DIN pins). 11 = TS0 serial input muxing enabled (muxed TS0_DIN7 with URXD1). Note: For proper device operation, when writing to this bit, only a "0" should be written. PCI Function Enable (see Section 4. 7. 3. 1, PCI, HPI, EMIFA and ATA Pin Muxing). Default value is determined by PCIEN boot configuration pin. HPI Function Enable (see Section 4. 7. 3. 1, PCI, HPI, EMIFA and ATA Pin Muxing). ATA Function Enable (see Section 4. 7. 3. 1, PCI, HPI, EMIFA and ATA Pin Muxing). DESCRIPTION 30 STCCK 29 AUDCK1 28 27 AUDCK0 RSV 26:24 CRGMUX 23:22 TSSOMUX 21:20 TSSIMUX 19:18 TSPOMUX 17:16 15:6 5 4:3 2 1 0 (1) TSPIMUX RESERVED RESERVED RESERVED PCIEN HPIEN ATAEN IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 4. 8. 1, Pullup/Pulldown Resistors. 112 Device Configurations Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 4. 7. 2. 2 PINMUX1 Register Description The Pin Multiplexing 1 Register controls the pin function in the UART0, UART1, and UART2 Blocks. The PINMUX1 register format is shown in Figure 4-19 and the bit field descriptions are given in Table 4-23. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX bit fields that control each muxed pin, see Section 4. 7. 3, Pin Multiplexing Details. For the pin-by-pin muxing control of the UART0, UART1, and UART2 Blocks, see Section 4. 7. 3. 8, UART0 Pin Muxing; Section 4. 7. 3. 9, UART1 Pin Muxing; and Section 4. 7. 3. 10, UART2 Pin Muxing. 31 RESERVED R-0000 0000 0000 0000 15 RESERVED R-0000 0000 00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 6 5 4 3 2 1 0 16 UART2CTL R/W-00 UART1CTL R/W-00 UART0CTL R/W-00 Figure 4-19. PINMUX1 Register Bit Descriptions BIT 31:6 NAME RESERVED Reserved. UART2 Pin Configuration (see Section 4. 7. 3. 10, UART2 Pin Muxing). [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]