User manual TEXAS INSTRUMENTS TMS320F28016 DATA MANUAL REV L

[. . . ] TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS230L October 2003 ­ Revised December 2009 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com Contents 1 F280x, F2801x, C280x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. STANDBY Mode: HALT Mode: NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712) for more details. 52 Functional Overview Copyright © 2003­2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www. ti. com SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 4 Peripherals The integrated peripherals of the 280x are described in the following subsections: · Three 32-bit CPU-Timers · Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6) · Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4) · Up to two enhanced QEP modules (eQEP1, eQEP2) · Enhanced analog-to-digital converter (ADC) module · Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B) · Up to two serial communications interface modules (SCI-A, SCI-B) · Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D) · Inter-integrated circuit module (I2C) · Digital I/O and shared pin functions 4. 1 32-Bit CPU-Timers 0/1/2 There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2). CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These timers are different from the timers that are present in the ePWM modules. NOTE If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application. Reset Timer Reload 16-Bit Timer Divide-Down TDDRH:TDDR 32-Bit Timer Period PRDH:PRD SYSCLKOUT TCR. 4 (Timer Start Status) 16-Bit Prescale Counter PSCH:PSC Borrow 32-Bit Counter TIMH:TIM Borrow TINT Figure 4-1. CPU-Timers Copyright © 2003­2009, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 53 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-2. INT1 to INT12 PIE TINT0 CPU-TIMER 0 C28x TINT1 INT13 XINT13 INT14 TINT2 CPU-TIMER 2 (Reserved for DSP/BIOS) CPU-TIMER 1 A. B. The timer registers are connected to the memory bus of the C28x processor. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4-2. CPU-Timer Interrupt Signals and Output Signal The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712). CPU-Timers 0, 1, 2 Configuration and Control Registers NAME TIMER0TIM TIMER0TIMH TIMER0PRD TIMER0PRDH TIMER0TCR Reserved TIMER0TPR TIMER0TPRH TIMER1TIM TIMER1TIMH TIMER1PRD TIMER1PRDH TIMER1TCR Reserved TIMER1TPR TIMER1TPRH TIMER2TIM TIMER2TIMH TIMER2PRD TIMER2PRDH TIMER2TCR ADDRESS 0x0C00 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C 0x0C0D 0x0C0E 0x0C0F 0x0C10 0x0C11 0x0C12 0x0C13 0x0C14 SIZE (x16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CPU-Timer 0, Counter Register CPU-Timer 0, Counter Register High CPU-Timer 0, Period Register CPU-Timer 0, Period Register High CPU-Timer 0, Control Register Reserved CPU-Timer 0, Prescale Register CPU-Timer 0, Prescale Register High CPU-Timer 1, Counter Register CPU-Timer 1, Counter Register High CPU-Timer 1, Period Register CPU-Timer 1, Period Register High CPU-Timer 1, Control Register Reserved CPU-Timer 1, Prescale Register CPU-Timer 1, Prescale Register High CPU-Timer 2, Counter Register CPU-Timer 2, Counter Register High CPU-Timer 2, Period Register CPU-Timer 2, Period Register High CPU-Timer 2, Control Register DESCRIPTION 54 Peripherals Copyright © 2003­2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www. ti. com SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 CPU-Timers 0, 1, 2 Configuration and Control Registers (continued) NAME Reserved TIMER2TPR TIMER2TPRH Reserved ADDRESS 0x0C15 0x0C16 0x0C17 0x0C18 ­ 0x0C3F SIZE (x16) 1 1 1 40 Reserved CPU-Timer 2, Prescale Register CPU-Timer 2, Prescale Register High Reserved DESCRIPTION 4. 2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) The 280x device contains up to six enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRU791) for more details. EPWM1SYNCI EPWM1INT EPWM1SOC EPWM1SYNCI EPWM1A ePWM1 module EPWM1B TZ1 to TZ6 to eCAP1 module (sync in) EPWM2INT PIE EPWM2SOC EPWM1SYNCO . EPWM1SYNCO EPWM2SYNCI EPWM2A ePWM2 module EPWM2B TZ1 to TZ6 GPIO MUX EPWM2SYNCO EPWMxSYNCI EPWMxINT EPWMxSOC ePWMx module EPWMxA EPWMxB TZ1 to TZ6 ADCSOCx0 Peripheral Bus EPWMxSYNCO ADC Figure 4-3. Multiple PWM Modules in a 280x System Table 4-2 shows the complete ePWM register set per module. Copyright © 2003­2009, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 55 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com Table 4-2. ePWM Control and Status Registers NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) (2) ePWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 ePWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 ePWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 ePWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 ePWM5 0x6900 0x6901 N/A 0x6903 0x6904 0x6905 0x6907 N/A 0x6909 0x690A 0x690B 0x690C 0x690D 0x690E 0x690F 0x6910 0x6911 0x6912 0x6914 0x6915 0x6916 0x6917 0x6918 0x6919 0x691A 0x691B 0x691C 0x691D 0x691E 0x6920 (2) ePWM6 0x6940 0x6941 N/A 0x6943 0x6944 0x6945 0x6947 N/A 0x6949 0x694A 0x694B 0x694C 0x694D 0x694E 0x694F 0x6950 0x6951 0x6952 0x6954 0x6955 0x6956 0x6957 0x6958 0x6959 0x695A 0x695B 0x695C 0x695D 0x695E 0x6960 (2) SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register (1) Trip Zone Control Register (1) Trip Zone Enable Interrupt Register (1) Trip Zone Flag Register Trip Zone Clear Register (1) Trip Zone Force Register (1) Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) Registers that are EALLOW protected. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]