User manual TEXAS INSTRUMENTS TMS320F28068 ADVANCE INFORMATION

[. . . ] TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www. ti. com SPRS698A ­ NOVEMBER 2010 ­ REVISED JANUARY 2011 Piccolo Microcontrollers Check for Samples: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 1 TMS320F2806x ( PiccoloTM) MCUs 1. 1 123 Features · Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts · Three 32-Bit CPU Timers · Advanced Control Peripherals · Up to 8 Enhanced Pulse Width Modulator (ePWM) Modules ­ 16 PWM Channels Total (8 HRPWM-Capable) ­ Independent 16-Bit Timer in Each Module · 3 Input Capture (eCAP) Modules · 4 High-Resolution Input Capture (HRCAP) Modules · 2 Quadrature Encoder (eQEP) Modules · 12-Bit ADC, Dual Sample-and-Hold ­ Up to 3 MSPS ­ Up to 16 Channels · On-Chip Temperature Sensor · 128-Bit Security Key/Lock ­ Protects Secure Memory Blocks ­ Prevents Firmware Reverse Engineering · Serial Port Peripherals ­ Up to Two Serial Communications Interface (SCI) [UART] Modules ­ Two Serial Peripheral Interface (SPI) Modules ­ One Inter-Integrated-Circuit (I2C) Bus ­ One Multi-Channel Buffered Serial Port (McBSP) Bus ­ One Enhanced Controller Area Network (eCAN) · Up to 54 Individually Programmable, Multiplexed GPIO Pins With Input Filtering · Advanced Emulation Features ­ Analysis and Breakpoint Functions ­ Real-Time Debug via Hardware · 2806x Packages ­ 80-Pin PFP and 100-Pin PZP PowerPADTM Low-Profile Quad Flatpacks (LQFPs) ­ 80-Pin PN and 100-Pin PZ LQFPs · High-Efficiency 32-Bit CPU (TMS320C28xTM) ­ 80 MHz (12. 5-ns Cycle Time) ­ 16 x 16 and 32 x 32 MAC Operations ­ 16 x 16 Dual MAC ­ Harvard Bus Architecture ­ Atomic Operations ­ Fast Interrupt Response and Processing ­ Unified Memory Programming Model ­ Code-Efficient (in C/C++ and Assembly) · Floating-Point Unit ­ Native Single-Precision Floating-Point Operations · Programmable Control Law Accelerator (CLA) ­ 32-Bit Floating-Point Math Accelerator ­ Executes Code Independently of the Main CPU · Viterbi, Complex Math, CRC Unit (VCU) ­ Extends C28xTM Instruction Set to Support Complex Multiply, Viterbi Operations, and Cyclic Redundency Check (CRC) · Embedded Memory ­ Up to 256KB Flash ­ Up to 100KB RAM ­ 2KB OTP ROM · 6-Channel DMA · Low Device and System Cost ­ Single 3. 3-V Supply ­ No Power Sequencing Requirement ­ Integrated Power-on Reset and Brown-out Reset ­ Low-Power Operating Modes ­ No Analog Support Pin · Clocking ­ Two Internal Zero-pin Oscillators ­ On-Chip Crystal Oscillator/External Clock Input ­ Dynamic PLL Ratio Changes Supported ­ Watchdog Timer Module ­ Missing Clock Detection Circuitry 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Piccolo, PowerPAD, C28x, TMS320C2000, C2000, Code Composer Studio, XDS510, XDS560, TMS320C28x, TMS320C54x, TMS320C55x are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 2 3 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2010­2011, Texas Instruments Incorporated ADVANCE INFORMATION TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A ­ NOVEMBER 2010 ­ REVISED JANUARY 2011 www. ti. com 1. 2 Description The F2806x PiccoloTM family of microcontrollers provides the power of the C28xTM core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. [. . . ] Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e. ti. com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Copyright © 2010­2011, Texas Instruments Incorporated Device and Documentation Support Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 57 ADVANCE INFORMATION TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A ­ NOVEMBER 2010 ­ REVISED JANUARY 2011 www. ti. com 5 Device Operating Conditions 5. 1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) Supply voltage range, VDD Analog voltage range, VDDA Input voltage range, VIN (3. 3 V) Output voltage range, VO Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3) Output clamp current, IOK (VO < 0 or VO > VDDIO) Junction temperature range, TJ (1) (2) (3) (4) (4) (4) with respect to VSS with respect to VSS with respect to VSSA ­0. 3 V to 4. 6 V ­0. 3 V to 2. 5 V ­0. 3 V to 4. 6 V ­0. 3 V to 4. 6 V ­0. 3 V to 4. 6 V ±20 mA ±20 mA ­40°C to 150°C ­65°C to 150°C Storage temperature range, Tstg Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5. 2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ± 2 mA. Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). ADVANCE INFORMATION 5. 2 Recommended Operating Conditions MIN NOM 3. 3 1. 8 0 2. 97 2 2 VSS ­ 0. 3 All GPIO/AIO pins Group 2 (2) All GPIO/AIO pins Group 2 (2) T version S version Q version (Q100 qualification) ­40 ­40 ­40 ­4 ­8 4 8 105 125 125 °C 3. 3 0 80 VDDIO + 0. 3 0. 8 3. 63 MAX 3. 63 1. 995 UNIT V V V V V MHz V V mA mA mA mA (1) Device supply voltage, I/O, VDDIO 2. 97 1. 71 Device supply voltage CPU, VDD (When internal VREG is disabled and 1. 8 V is supplied externally) Supply ground, VSS Analog supply voltage, VDDA (1) Analog ground, VSSA Device clock frequency (system clock) High-level input voltage, VIH (3. 3 V) Low-level input voltage, VIL (3. 3 V) High-level output source current, VOH = VOH(MIN) , IOH Low-level output sink current, VOL = VOL(MAX), IOL Junction temperature, TJ (3) (1) (2) (3) VDDIO and VDDA should be maintained within ~0. 3 V of each other. Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37. TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. 58 Device Operating Conditions Copyright © 2010­2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www. ti. com SPRS698A ­ NOVEMBER 2010 ­ REVISED JANUARY 2011 5. 3 Electrical Characteristics (1) PARAMETER TEST CONDITIONS IOH = IOH MAX IOH = 50 mA IOL = IOL MAX VDDIO = 3. 3 V, VIN = 0 V VDDIO = 3. 3 V, VIN = 0 V VDDIO = 3. 3 V, VIN = VDDIO VDDIO = 3. 3 V, VIN = VDDIO VO = VDDIO or 0 V 2 Falling VDDIO Time after BOR/POR/OVR event is removed to XRS release Internal VREG on 2. 50 2. 78 35 400 1. 9 800 2. 96 28 50 All GPIO/AIO XRS pin ­80 ­230 ­140 ­300 MIN 2. 4 VDDIO ­ 0. 2 0. 4 ­205 ­375 ±2 ±2 mA 80 ±2 mA pF mV ms V mA TYP MAX UNIT V V over recommended operating conditions (unless otherwise noted) VOH VOL High-level output voltage Low-level output voltage Input current (low level) Pin with pullup enabled Pin with pulldown enabled Pin with pullup enabled Pin with pulldown enabled IIL IIH Input current (high level) IOZ CI Output current, pullup or pulldown disabled Input capacitance VDDIO BOR trip point VDDIO BOR hysteresis Supervisor reset release delay time VREG VDD output (1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage (VDD) go out of range. Copyright © 2010­2011, Texas Instruments Incorporated Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 59 ADVANCE INFORMATION V TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A ­ NOVEMBER 2010 ­ REVISED JANUARY 2011 www. ti. com 6 Peripheral and Electrical Specifications 6. 1 6. 1. 1 Parameter Information Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: a c d f h r su t v w access time cycle time (period) delay time fall time hold time rise time setup time transition time valid time pulse duration (width) Letters and symbols and their meanings: H L V X Z High Low Valid Unknown, changing, or don't care level High impedance ADVANCE INFORMATION 6. 1. 2 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6. 2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. Tester Pin Electronics Data Sheet Timing Reference Point 42 W 3. 5 nH Transmission Line Z0 = 50 W (A) Output Under Test Device Pin (B) 4. 0 pF 1. 85 pF A. B. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]