User manual TEXAS INSTRUMENTS TMS320F28332 DATA MANUAL

[. . . ] TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS439I June 2007 ­ Revised March 2011 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439I ­ JUNE 2007 ­ REVISED MARCH 2011 www. ti. com Contents 1 TMS320F2833x, TMS320F2823x DSCs 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Figure 4-7 shows the block diagram of the eQEP module. System Control Registers To CPU EQEPxENCLK QCPRD QCAPCTL 16 16 QCTMRLAT QCPRDLAT QUTMR QUPRD 32 QEPCTL QEPSTS QFLG UTIME UTOUT QWDOG WDTOUT PIE EQEPxINT 16 QPOSLAT QPOSSLAT QPOSILAT 32 QPOSCNT QPOSINIT QPOSMAX 32 QPOSCMP 16 QEINT QFRC QCLR QPOSCTL Enhanced QEP (eQEP) Peripheral Position Counter/ Control Unit (PCCU) QCLK QDIR QI QS Quadrature Decoder PHE (QDU) PCSOUT QDECCTL 16 EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxI EQEPxS QWDTMR QWDPRD 16 Quadrature Capture Unit (QCAP) QCTMR 16 Registers Used by Multiple Units Figure 4-7. eQEP Functional Block Diagram 76 Peripherals Data Bus SYSCLKOUT Copyright © 2007­2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www. ti. com SPRS439I ­ JUNE 2007 ­ REVISED MARCH 2011 Table 4-5 provides a summary of the eQEP registers. eQEP Control and Status Registers NAME QPOSCNT QPOSINIT QPOSMAX QPOSCMP QPOSILAT QPOSSLAT QPOSLAT QUTMR QUPRD QWDTMR QWDPRD QDECCTL QEPCTL QCAPCTL QPOSCTL QEINT QFLG QCLR QFRC QEPSTS QCTMR QCPRD QCTMRLAT QCPRDLAT Reserved eQEP1 ADDRESS 0x6B00 0x6B02 0x6B04 0x6B06 0x6B08 0x6B0A 0x6B0C 0x6B0E 0x6B10 0x6B12 0x6B13 0x6B14 0x6B15 0x6B16 0x6B17 0x6B18 0x6B19 0x6B1A 0x6B1B 0x6B1C 0x6B1D 0x6B1E 0x6B1F 0x6B20 0x6B21 ­ 0x6B3F eQEP2 ADDRESS 0x6B40 0x6B42 0x6B44 0x6B46 0x6B48 0x6B4A 0x6B4C 0x6B4E 0x6B50 0x6B52 0x6B53 0x6B54 0x6B55 0x6B56 0x6B57 0x6B58 0x6B59 0x6B5A 0x6B5B 0x6B5C 0x6B5D 0x6B5E 0x6B5F 0x6B60 0x6B61 ­ 0x6B7F eQEP1 SIZE(x16)/ #SHADOW 2/0 2/0 2/0 2/1 2/0 2/0 2/0 2/0 2/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 31/0 REGISTER DESCRIPTION eQEP Position Counter eQEP Initialization Position Count eQEP Maximum Position Count eQEP Position-compare eQEP Index Position Latch eQEP Strobe Position Latch eQEP Position Latch eQEP Unit Timer eQEP Unit Period Register eQEP Watchdog Timer eQEP Watchdog Period Register eQEP Decoder Control Register eQEP Control Register eQEP Capture Control Register eQEP Position-compare Control Register eQEP Interrupt Enable Register eQEP Interrupt Flag Register eQEP Interrupt Clear Register eQEP Interrupt Force Register eQEP Status Register eQEP Capture Timer eQEP Capture Period Register eQEP Capture Timer Latch eQEP Capture Period Latch Copyright © 2007­2011, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 77 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439I ­ JUNE 2007 ­ REVISED MARCH 2011 www. ti. com 4. 7 Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-8. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: · 12-bit ADC core with built-in S/H · Analog input: 0. 0 V to 3. 0 V (Voltages above 3. 0 V produce full-scale conversion results. ) · Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12. 5 MSPS · 16 dedicated ADC channels. 8 channels multiplexed per Sample/Hold · Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 16 input channels · Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i. e. , two cascaded 8-state sequencers) · Sixteen result registers (individually addressable) to store conversion values ­ The digital value of the input analog voltage is derived by: Digital Value = 0, Digital Value = 4096 ´ Input Analog Voltage - ADCLO 3 when input £ 0 V when 0 V < input < 3 V when input ³ 3 V Digital Value = 4095, · · · · · Multiple triggers as sources for the start-of-conversion (SOC) sequence ­ S/W - software immediate start ­ ePWM start of conversion ­ XINT2 ADC start of conversion Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS. Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions. SOCA and SOCB triggers can operate independently in dual-sequencer mode. Sample-and-hold (S/H) acquisition time window has separate prescale control. The ADC module in the 2833x/2823x devices has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-8 shows the block diagram of the ADC module. The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results. 78 Peripherals Copyright © 2007­2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www. ti. com SPRS439I ­ JUNE 2007 ­ REVISED MARCH 2011 System Control Block HALT High-Speed Prescaler SYSCLKOUT DSP ADCENCLK Analog MUX ADCINA0 S/H ADCINA7 HSPCLK Result Registers Result Reg 0 Result Reg 1 70A8h 12-Bit ADC Module Result Reg 7 Result Reg 8 70AFh 70B0h ADCINB0 S/H ADCINB7 Result Reg 15 70B7h ADC Control Registers S/W EPWMSOCA GPIO/ XINT2_ADCSOC SOC Sequencer 1 Sequencer 2 SOC S/W EPWMSOCB Figure 4-8. Block Diagram of the ADC Module To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]