User manual TEXAS INSTRUMENTS TMS320VC5401 DATA MANUAL REV D

[. . . ] TMS320VC5401 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS153D December 2000 - Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS153C device-specific data sheet to make it an SPRS153D revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following changes. PAGE(S) NO. [. . . ] A major enhancement to the 5401 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The HPI8 memory map (see Figure 3-8) is identical to that of the DMA controller shown in Figure 3-10. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always synchronized to the 5401 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE states, and host accesses are not allowed while the 5401 reset pin is asserted. 28 SPRS153D December 2000 - Revised October 2008 Functional Overview The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers -- HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the 5401. Hex 0000 001F 0020 0023 0024 005F 0060 007F 0080 0FFF 1000 1FFF 2000 2FFF 3000 Reserved FFFF The scratch-pad RAM area is physically a part of the DARAM block starting at address 1000h. Physical location can affect multiple access performance. (See Section 3. 1. 2) Reserved McBSP Registers Reserved Scratch-Pad RAM Reserved On-Chip DARAM (4K x 16-bit) On-Chip DARAM (4K x 16-bit) Figure 3-8. HPI8 Memory Map December 2000 - Revised October 2008 SPRS153D 29 Functional Overview 3. 5 Multichannel Buffered Serial Ports (McBSPs) The 5401 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP provides: · · · Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: · Direct interface to: - - - - · · · · · T1/E1 framers MVIP switching compatible and ST-BUS compliant devices IOM-2 compliant devices Serial peripheral interface devices Multichannel transmit and receive of up to 128 channels A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits µ-law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins: · · · · · · BCLKX BDX BFSX BCLKR BDR BFSR Transmit reference clock Transmit data Transmit frame synchronization Receive reference clock Receive data Receive frame synchronization The six pins listed are functionally equivalent to previous serial port interface pins in the TMS320C5000t platform of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress. On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If the DRR is empty, the RBR contents are copied into the DRR. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]